in CMake-armcc/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c [3307:3533]
static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency)
{
uint32_t frequency = 0U;
uint32_t srcclk = 0U;
uint32_t pllvco, plln; /* no init needed */
#if defined(RCC_PLLP_SUPPORT)
uint32_t pllp = 0U;
#endif /* RCC_PLLP_SUPPORT */
/* Handle SAIs */
if(PeriphClk == RCC_PERIPHCLK_SAI1)
{
srcclk = __HAL_RCC_GET_SAI1_SOURCE();
if(srcclk == RCC_SAI1CLKSOURCE_PIN)
{
frequency = EXTERNAL_SAI1_CLOCK_VALUE;
}
/* Else, PLL clock output to check below */
}
#if defined(SAI2)
else
{
if(PeriphClk == RCC_PERIPHCLK_SAI2)
{
srcclk = __HAL_RCC_GET_SAI2_SOURCE();
if(srcclk == RCC_SAI2CLKSOURCE_PIN)
{
frequency = EXTERNAL_SAI2_CLOCK_VALUE;
}
/* Else, PLL clock output to check below */
}
}
#endif /* SAI2 */
if(frequency == 0U)
{
pllvco = InputFrequency;
#if defined(SAI2)
if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != 0U))
{
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
/* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U))
{
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
/* f(PLLSAI1 Source) / PLLSAI1M */
pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
#else
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
#endif
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI))
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
frequency = HSI_VALUE;
}
}
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#else
if(srcclk == RCC_SAI1CLKSOURCE_PLL)
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != 0U))
{
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
/* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
/* HSI automatically selected as clock source if PLLs not enabled */
frequency = HSI_VALUE;
}
else
{
/* No clock source, frequency default init at 0 */
}
}
else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && (__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != 0U))
{
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
/* PLLSAI1M exists: apply PLLSAI1M divider for PLLSAI1 output computation */
/* f(PLLSAI1 Source) / PLLSAI1M */
pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U));
#else
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
#endif
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != 0U)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
/* HSI automatically selected as clock source if PLLs not enabled */
frequency = HSI_VALUE;
}
else
{
/* No clock source, frequency default init at 0 */
}
}
#endif /* SAI2 */
#if defined(RCC_PLLSAI2_SUPPORT)
else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI2RDY) && (__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != 0U))
{
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
/* PLLSAI2M exists: apply PLLSAI2M divider for PLLSAI2 output computation */
/* f(PLLSAI2 Source) / PLLSAI2M */
pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U));
#else
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
#endif
/* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos;
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != 0U)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
#endif /* RCC_PLLSAI2_SUPPORT */
else
{
/* No clock source, frequency default init at 0 */
}
}
return frequency;
}