Path	Lines of Code
ERRATA.md	41
FAQs.md	305
README.md	168
RELEASE_NOTES.md	457
SDAccel/ERRATA.md	5
SDAccel/FAQ.md	81
SDAccel/README.md	168
SDAccel/examples/aws/data_retention/src/vaddx4.cl	54
SDAccel/examples/aws/data_retention/src/vmul_vadd_x4.cpp	178
SDAccel/examples/aws/data_retention/src/vmulx4.cl	54
SDAccel/examples/aws/helloworld_ocl_runtime/2018.3_2019.1/sdaccel.ini	2
SDAccel/examples/aws/helloworld_ocl_runtime/README.md	37
SDAccel/examples/aws/helloworld_ocl_runtime/sdaccel.ini	2
SDAccel/examples/aws/kernel_3ddr_bandwidth/README.md	66
SDAccel/examples/aws/kernel_3ddr_bandwidth/description.json	41
SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel.cl	27
SDAccel/examples/aws/kernel_3ddr_bandwidth/src/kernel_global_bandwidth.cpp	156
SDAccel/userspace/README.md	16
SDAccel/userspace/RELEASE_NOTES.md	9
SDAccel/userspace/src/README.md	17
Vitis/README.md	163
developer_resources/DCV.md	88
developer_resources/DCV_with_ParallelCluster.md	322
developer_resources/README.md	11
hdk/README.md	275
hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.md	8
hdk/cl/developer_designs/Starting_Your_Own_CL.md	39
hdk/cl/examples/cl_dram_dma/README.md	102
hdk/cl/examples/cl_dram_dma/build/README.md	118
hdk/cl/examples/cl_dram_dma/build/scripts/aws_build_dcp_from_cl.sh	191
hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl	337
hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl	59
hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl	105
hdk/cl/examples/cl_dram_dma/build/scripts/top_ddr_fix.tcl	34
hdk/cl/examples/cl_dram_dma/design/axil_slave.sv	129
hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv	1413
hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv	666
hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_axi_mstr.sv	301
hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh	50
hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_pkg.sv	75
hdk/cl/examples/cl_dram_dma/design/cl_id_defines.vh	29
hdk/cl/examples/cl_dram_dma/design/cl_ila.sv	156
hdk/cl/examples/cl_dram_dma/design/cl_int_slv.sv	50
hdk/cl/examples/cl_dram_dma/design/cl_int_tst.sv	178
hdk/cl/examples/cl_dram_dma/design/cl_ocl_slv.sv	313
hdk/cl/examples/cl_dram_dma/design/cl_pcim_mstr.sv	128
hdk/cl/examples/cl_dram_dma/design/cl_sda_slv.sv	86
hdk/cl/examples/cl_dram_dma/design/cl_tst.sv	1225
hdk/cl/examples/cl_dram_dma/design/cl_tst_scrb.sv	367
hdk/cl/examples/cl_dram_dma/design/cl_vio.sv	86
hdk/cl/examples/cl_dram_dma/design/mem_scrb.sv	126
hdk/cl/examples/cl_dram_dma/software/include/cl_dram_dma.h	1
hdk/cl/examples/cl_dram_dma/software/include/sh_dpi_tasks.h	40
hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c	253
hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.c	123
hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_common.h	9
hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_hwsw_cosim.c	179
hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma_retention.c	124
hdk/cl/examples/cl_dram_dma/software/src/test_dram_dma.c	47
hdk/cl/examples/cl_dram_dma/software/src/test_null.c	10
hdk/cl/examples/cl_dram_dma/verif/README.md	97
hdk/cl/examples/cl_dram_dma/verif/scripts/top.ies.f	74
hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f	73
hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f	69
hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f	89
hdk/cl/examples/cl_dram_dma/verif/scripts/waves.tcl	25
hdk/cl/examples/cl_dram_dma/verif/tests/test_axi_mstr_multi_rw.sv	312
hdk/cl/examples/cl_dram_dma/verif/tests/test_bar1.sv	76
hdk/cl/examples/cl_dram_dma/verif/tests/test_clk_recipe.sv	156
hdk/cl/examples/cl_dram_dma/verif/tests/test_ddr.sv	167
hdk/cl/examples/cl_dram_dma/verif/tests/test_ddr_peek_bdr_walking_ones.sv	149
hdk/cl/examples/cl_dram_dma/verif/tests/test_ddr_peek_poke.sv	87
hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcim_concurrent.sv	251
hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_pcis_concurrent.sv	150
hdk/cl/examples/cl_dram_dma/verif/tests/test_dma_sda_concurrent.sv	188
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma.sv	225
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_4k_crossing.sv	219
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_allgn_addr_4k.sv	217
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_axi_mstr.sv	277
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_bdr_common.svh	59
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_dram_bdr_row_col_combo.sv	93
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_dram_bdr_wr.sv	75
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_mem_model_bdr_rd.sv	160
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_mem_model_bdr_wr.sv	169
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_multi_ddr.sv	208
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_rnd.sv	207
hdk/cl/examples/cl_dram_dma/verif/tests/test_dram_dma_single_beat_4k.sv	218
hdk/cl/examples/cl_dram_dma/verif/tests/test_host_pcim.sv	181
hdk/cl/examples/cl_dram_dma/verif/tests/test_int.sv	91
hdk/cl/examples/cl_dram_dma/verif/tests/test_null.sv	24
hdk/cl/examples/cl_dram_dma/verif/tests/test_peek_poke.sv	162
hdk/cl/examples/cl_dram_dma/verif/tests/test_peek_poke_len.sv	167
hdk/cl/examples/cl_dram_dma/verif/tests/test_peek_poke_pcis_axsize.sv	91
hdk/cl/examples/cl_dram_dma/verif/tests/test_peek_poke_rnd_lengths.sv	152
hdk/cl/examples/cl_dram_dma/verif/tests/test_peek_poke_wc.sv	116
hdk/cl/examples/cl_dram_dma/verif/tests/test_sda.sv	69
hdk/cl/examples/cl_dram_dma_hlx/README.md	103
hdk/cl/examples/cl_dram_dma_hlx/build/scripts/aws_build_dcp_from_cl.sh	154
hdk/cl/examples/cl_dram_dma_hlx/build/scripts/create_dcp_from_cl.tcl	62
hdk/cl/examples/cl_examples_list.md	23
hdk/cl/examples/cl_hello_world/README.md	45
hdk/cl/examples/cl_hello_world/build/README.md	118
hdk/cl/examples/cl_hello_world/build/scripts/aws_build_dcp_from_cl.sh	191
hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl	318
hdk/cl/examples/cl_hello_world/build/scripts/encrypt.tcl	52
hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl	97
hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv	402
hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh	24
hdk/cl/examples/cl_hello_world/design/cl_id_defines.vh	29
hdk/cl/examples/cl_hello_world/software/runtime/test_hello_world.c	187
hdk/cl/examples/cl_hello_world/software/verif_rtl/include/sh_dpi_tasks.h	40
hdk/cl/examples/cl_hello_world/software/verif_rtl/src/test_hello_world.c	28
hdk/cl/examples/cl_hello_world/software/verif_rtl/src/test_null.c	12
hdk/cl/examples/cl_hello_world/verif/README.md	31
hdk/cl/examples/cl_hello_world/verif/scripts/top.ies.f	63
hdk/cl/examples/cl_hello_world/verif/scripts/top.questa.f	63
hdk/cl/examples/cl_hello_world/verif/scripts/top.vcs.f	61
hdk/cl/examples/cl_hello_world/verif/scripts/top.vivado.f	59
hdk/cl/examples/cl_hello_world/verif/scripts/waves.tcl	25
hdk/cl/examples/cl_hello_world/verif/tests/test_gl_cntr.sv	56
hdk/cl/examples/cl_hello_world/verif/tests/test_hello_world.sv	52
hdk/cl/examples/cl_hello_world/verif/tests/test_null.sv	24
hdk/cl/examples/cl_hello_world_hlx/README.md	109
hdk/cl/examples/cl_hello_world_hlx/build/scripts/aws_build_dcp_from_cl.sh	154
hdk/cl/examples/cl_hello_world_hlx/build/scripts/create_dcp_from_cl.tcl	62
hdk/cl/examples/cl_hello_world_ref_hlx/README.md	86
hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/aws_build_dcp_from_cl.sh	124
hdk/cl/examples/cl_hello_world_ref_hlx/build/scripts/create_dcp_from_cl.tcl	58
hdk/cl/examples/cl_hello_world_vhdl/README.md	57
hdk/cl/examples/cl_hello_world_vhdl/build/README.md	118
hdk/cl/examples/cl_hello_world_vhdl/build/scripts/aws_build_dcp_from_cl.sh	191
hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl	313
hdk/cl/examples/cl_hello_world_vhdl/build/scripts/encrypt.tcl	51
hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl	106
hdk/cl/examples/cl_hello_world_vhdl/design/cl_hello_world.sv	854
hdk/cl/examples/cl_hello_world_vhdl/design/cl_hello_world_defines.vh	31
hdk/cl/examples/cl_hello_world_vhdl/design/cl_hello_world_pkg.sv	72
hdk/cl/examples/cl_hello_world_vhdl/design/cl_id_defines.vh	29
hdk/cl/examples/cl_hello_world_vhdl/design/cl_vhdl_wrapper.vhd	714
hdk/cl/examples/cl_hello_world_vhdl/design/hello_world.sv	179
hdk/cl/examples/cl_hello_world_vhdl/software/runtime/test_hello_world_vhdl.c	187
hdk/cl/examples/cl_hello_world_vhdl/software/verif_rtl/include/sh_dpi_tasks.h	29
hdk/cl/examples/cl_hello_world_vhdl/software/verif_rtl/src/test_hello_world.c	34
hdk/cl/examples/cl_hello_world_vhdl/software/verif_rtl/src/test_null.c	12
hdk/cl/examples/cl_hello_world_vhdl/verif/README.md	11
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top.questa.f	62
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top.vcs.f	63
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top.vivado.f	60
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top_vhdl.questa.f	15
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top_vhdl.vcs.f	15
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/top_vhdl.vivado.f	1
hdk/cl/examples/cl_hello_world_vhdl/verif/scripts/waves.tcl	25
hdk/cl/examples/cl_hello_world_vhdl/verif/tests/test_hello_world.sv	48
hdk/cl/examples/cl_hello_world_vhdl/verif/tests/test_null.sv	24
hdk/cl/examples/cl_hls_dds_hlx/README.md	81
hdk/cl/examples/cl_hls_dds_hlx/build/scripts/aws_build_dcp_from_cl.sh	124
hdk/cl/examples/cl_hls_dds_hlx/build/scripts/create_dcp_from_cl.tcl	58
hdk/cl/examples/cl_ipi_cdma_test_hlx/README.md	88
hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/aws_build_dcp_from_cl.sh	124
hdk/cl/examples/cl_ipi_cdma_test_hlx/build/scripts/create_dcp_from_cl.tcl	58
hdk/cl/examples/cl_sde/README.md	66
hdk/cl/examples/cl_sde/build/scripts/aws_build_dcp_from_cl.sh	191
hdk/cl/examples/cl_sde/build/scripts/create_dcp_from_cl.tcl	320
hdk/cl/examples/cl_sde/build/scripts/encrypt.tcl	73
hdk/cl/examples/cl_sde/build/scripts/synth_cl_sde.tcl	105
hdk/cl/examples/cl_sde/design/axi_prot_chk.sv	154
hdk/cl/examples/cl_sde/design/cl_id_defines.vh	29
hdk/cl/examples/cl_sde/design/cl_pkt_tst.sv	912
hdk/cl/examples/cl_sde/design/cl_sde.sv	1098
hdk/cl/examples/cl_sde/design/cl_sde_defines.vh	25
hdk/cl/examples/cl_sde/design/cl_sde_srm.sv	287
hdk/cl/examples/cl_sde/design/cl_tst.sv	1213
hdk/cl/examples/cl_sde/design/ila_axi4_wrapper.sv	279
hdk/cl/examples/cl_sde/design/sde.sv	673
hdk/cl/examples/cl_sde/design/sde_c2h.sv	524
hdk/cl/examples/cl_sde/design/sde_c2h_axis.sv	67
hdk/cl/examples/cl_sde/design/sde_c2h_buf.sv	343
hdk/cl/examples/cl_sde/design/sde_c2h_cfg.sv	786
hdk/cl/examples/cl_sde/design/sde_c2h_data.sv	1081
hdk/cl/examples/cl_sde/design/sde_desc.sv	393
hdk/cl/examples/cl_sde/design/sde_h2c.sv	509
hdk/cl/examples/cl_sde/design/sde_h2c_axis.sv	66
hdk/cl/examples/cl_sde/design/sde_h2c_buf.sv	509
hdk/cl/examples/cl_sde/design/sde_h2c_cfg.sv	720
hdk/cl/examples/cl_sde/design/sde_h2c_data.sv	794
hdk/cl/examples/cl_sde/design/sde_pkg.sv	292
hdk/cl/examples/cl_sde/design/sde_pm.sv	514
hdk/cl/examples/cl_sde/design/sde_ps.sv	698
hdk/cl/examples/cl_sde/design/sde_ps_acc.sv	236
hdk/cl/examples/cl_sde/design/sde_wb.sv	688
hdk/cl/examples/cl_sde/ip/cl_sde_ip_setup.tcl	22
hdk/cl/examples/cl_sde/ip/device_type.tcl	7
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_axi4/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_axi4/ila_axi4.veo	87
hdk/cl/examples/cl_sde/ip/ila_axi4/ila_axi4.xml	74868
hdk/cl/examples/cl_sde/ip/ila_axi4/sim/ila_axi4.v	1
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_axi4_512/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_axi4_512/ila_axi4_512.veo	87
hdk/cl/examples/cl_sde/ip/ila_axi4_512/ila_axi4_512.xml	74882
hdk/cl/examples/cl_sde/ip/ila_axi4_512/sim/ila_axi4_512.v	1
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/ila_v6_2_syn_rfs.v	7823
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/ltlib_v1_0_vl_rfs.v	1185
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_axis/hdl/xsdbs_v1_0_vl_rfs.v	501
hdk/cl/examples/cl_sde/ip/ila_axis/ila_axis.veo	64
hdk/cl/examples/cl_sde/ip/ila_axis/ila_axis.xml	74835
hdk/cl/examples/cl_sde/ip/ila_axis/sim/ila_axis.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.veo	76
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/ila_sde_c2h_buf.xml	74866
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_buf/sim/ila_sde_c2h_buf.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.veo	122
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/ila_sde_c2h_dm.xml	74861
hdk/cl/examples/cl_sde/ip/ila_sde_c2h_dm/sim/ila_sde_c2h_dm.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.veo	87
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/ila_sde_h2c_buf.xml	74847
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_buf/sim/ila_sde_h2c_buf.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.veo	109
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/ila_sde_h2c_dm.xml	74848
hdk/cl/examples/cl_sde/ip/ila_sde_h2c_dm/sim/ila_sde_h2c_dm.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/ila_v6_2_syn_rfs.v	7823
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/ltlib_v1_0_vl_rfs.v	1185
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_ps/hdl/xsdbs_v1_0_vl_rfs.v	501
hdk/cl/examples/cl_sde/ip/ila_sde_ps/ila_sde_ps.veo	105
hdk/cl/examples/cl_sde/ip/ila_sde_ps/ila_sde_ps.xml	74850
hdk/cl/examples/cl_sde/ip/ila_sde_ps/sim/ila_sde_ps.v	1
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/blk_mem_gen_v8_3_vhsyn_rfs.vhd	193141
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/fifo_generator_v13_1_vhsyn_rfs.vhd	31617
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/ila_v6_2_syn_rfs.v	7819
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/ltlib_v1_0_vl_rfs.v	1184
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_in.vh	1043
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_lib_fn.vh	115
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_param.vh	3145
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ila_v6_2_5_ila_ver.vh	112
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ltlib_v1_0_0_lib_fn.vh	97
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/ltlib_v1_0_0_ver.vh	93
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_core.vh	609
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_core_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_ports.vh	176
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bs_vec.vh	490
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bsid_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_bsid_vec_ports.vh	16
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_icn.vh	33
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_id_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_id_vec_map.vh	192
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_in.vh	99
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbm_v3_0_0_sl_prt_map.vh	512
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_i2x.vh	43
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/verilog/xsdbs_v1_0_2_in.vh	94
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/xsdbm_v3_0_vl_rfs.v	8684
hdk/cl/examples/cl_sde/ip/ila_sde_wb/hdl/xsdbs_v1_0_vl_rfs.v	500
hdk/cl/examples/cl_sde/ip/ila_sde_wb/ila_sde_wb.veo	107
hdk/cl/examples/cl_sde/ip/ila_sde_wb/ila_sde_wb.xml	74855
hdk/cl/examples/cl_sde/ip/ila_sde_wb/sim/ila_sde_wb.v	1
hdk/cl/examples/cl_sde/lib/axis_flop_fifo.sv	103
hdk/cl/examples/cl_sde/lib/bram_1w1r.sv	89
hdk/cl/examples/cl_sde/lib/flop_fifo_in.sv	140
hdk/cl/examples/cl_sde/lib/ft_fifo.v	57
hdk/cl/examples/cl_sde/lib/ft_fifo_p.v	57
hdk/cl/examples/cl_sde/lib/ram_fifo_ft.sv	108
hdk/cl/examples/cl_sde/lib/rr_arb.sv	77
hdk/cl/examples/cl_sde/software/include/sh_dpi_tasks.h	40
hdk/cl/examples/cl_sde/software/src/test_null.c	10
hdk/cl/examples/cl_sde/verif/scripts/top.ies.f	107
hdk/cl/examples/cl_sde/verif/scripts/top.questa.f	106
hdk/cl/examples/cl_sde/verif/scripts/top.vcs.f	106
hdk/cl/examples/cl_sde/verif/scripts/top.vivado.f	108
hdk/cl/examples/cl_sde/verif/scripts/waves.tcl	25
hdk/cl/examples/cl_sde/verif/tests/test_base.inc	617
hdk/cl/examples/cl_sde/verif/tests/test_null.sv	24
hdk/cl/examples/cl_sde/verif/tests/test_simple_c2h.sv	127
hdk/cl/examples/cl_sde/verif/tests/test_simple_h2c.sv	149
hdk/cl/examples/cl_uram_example/README.md	100
hdk/cl/examples/cl_uram_example/build/README.md	118
hdk/cl/examples/cl_uram_example/build/scripts/aws_build_dcp_from_cl.sh	191
hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl	315
hdk/cl/examples/cl_uram_example/build/scripts/encrypt.tcl	53
hdk/cl/examples/cl_uram_example/build/scripts/synth_cl_uram_example.tcl	124
hdk/cl/examples/cl_uram_example/design/cl_id_defines.vh	29
hdk/cl/examples/cl_uram_example/design/cl_uram_example.sv	383
hdk/cl/examples/cl_uram_example/design/cl_uram_example_defines.vh	26
hdk/cl/examples/cl_uram_example/design/ctrl_uram.vhd	243
hdk/cl/examples/cl_uram_example/software/runtime/test_uram_example.c	248
hdk/cl/examples/cl_uram_example/verif/README.md	31
hdk/cl/examples/cl_uram_example/verif/scripts/top.ies.f	63
hdk/cl/examples/cl_uram_example/verif/scripts/top.questa.f	65
hdk/cl/examples/cl_uram_example/verif/scripts/top.vcs.f	62
hdk/cl/examples/cl_uram_example/verif/scripts/top.vivado.f	60
hdk/cl/examples/cl_uram_example/verif/scripts/waves.tcl	25
hdk/cl/examples/cl_uram_example/verif/tests/test_null.sv	24
hdk/cl/examples/cl_uram_example/verif/tests/test_uram_example.sv	109
hdk/cl/examples/common/design/cl_common_defines.vh	22
hdk/cl/examples/hello_world_hlx/README.md	84
hdk/cl/examples/hello_world_hlx/build/scripts/aws_build_dcp_from_cl.sh	124
hdk/cl/examples/hello_world_hlx/build/scripts/create_dcp_from_cl.tcl	58
hdk/common/README.md	18
hdk/common/shell_stable/design/interfaces/README.md	2
hdk/common/shell_stable/design/ip/axi_clock_converter_0/axi_clock_converter_0.xml	4300
hdk/common/shell_stable/design/ip/axi_register_slice/axi_register_slice.xml	4405
hdk/common/shell_stable/design/ip/axi_register_slice_light/axi_register_slice_light.xml	4433
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xml	1652
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml	4429
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xml	4429
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xml	4429
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/cl_axi_interconnect_m03_regslice_0.xml	4429
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0.xml	4443
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0.xml	4443
hdk/common/shell_stable/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/cl_axi_interconnect_xbar_0.xml	44007
hdk/common/shell_stable/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml	4429
hdk/common/shell_stable/design/ip/cl_debug_bridge/bd_0/ip/ip_0/bd_a493_xsdbm_0.xml	22275
hdk/common/shell_stable/design/ip/cl_debug_bridge/bd_0/ip/ip_1/bd_a493_lut_buffer_0.xml	1019
hdk/common/shell_stable/design/ip/cl_debug_bridge/cl_debug_bridge.xml	890
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_0/bd_bf3f_microblaze_I_0.xml	27479
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_1/bd_bf3f_rst_0_0.xml	786
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_2/bd_bf3f_ilmb_0.xml	3476
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_3/bd_bf3f_dlmb_0.xml	3478
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_4/bd_bf3f_dlmb_cntlr_0.xml	4073
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_5/bd_bf3f_ilmb_cntlr_0.xml	4073
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_6/bd_bf3f_lmb_bram_I_0.xml	4240
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_7/bd_bf3f_second_dlmb_cntlr_0.xml	4073
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_8/bd_bf3f_second_ilmb_cntlr_0.xml	4073
hdk/common/shell_stable/design/ip/ddr4_core/bd_0/ip/ip_9/bd_bf3f_second_lmb_bram_I_0.xml	4240
hdk/common/shell_stable/design/ip/ddr4_core/ddr4_core.xml	9300
hdk/common/shell_stable/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs.xml	2331
hdk/common/shell_stable/design/ip/ddr4_core/ip_1/ddr4_core_phy.xml	5105
hdk/common/shell_stable/design/ip/dest_register_slice/dest_register_slice.xml	4406
hdk/common/shell_stable/design/ip/ila_0/ila_0.xml	74834
hdk/common/shell_stable/design/ip/ila_1/ila_1.xml	74847
hdk/common/shell_stable/design/ip/ila_vio_counter/ila_vio_counter.xml	74839
hdk/common/shell_stable/design/ip/src_register_slice/src_register_slice.xml	4406
hdk/common/shell_stable/design/ip/vio_0/vio_0.xml	20790
hdk/common/shell_stable/hlx/design/boards/board.xml	13
hdk/common/shell_stable/hlx/design/ip/aws_v1_0/component.xml	16542
hdk/common/shell_stable/hlx/design/ip/aws_v1_0/interface/aws_f1_sh1.xml	11
hdk/common/shell_stable/hlx/design/ip/aws_v1_0/interface/aws_f1_sh1_rtl.xml	2890
hdk/common/shell_stable/hlx/hlx_examples/build/IPI/cl_hello_world_ref/design.xml	10
hdk/common/shell_stable/hlx/hlx_examples/build/IPI/cl_hls_dds/design.xml	10
hdk/common/shell_stable/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/design.xml	10
hdk/common/shell_stable/hlx/hlx_examples/build/IPI/hello_world/design.xml	10
hdk/common/shell_stable/hlx/hlx_examples/build/RTL/cl_dram_dma/design.xml	10
hdk/common/shell_stable/hlx/hlx_examples/build/RTL/cl_hello_world/design.xml	10
hdk/common/shell_stable/new_cl_template/build/README.md	118
hdk/common/shell_v04261818/design/interfaces/README.md	2
hdk/common/shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.xml	4300
hdk/common/shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xml	4405
hdk/common/shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xml	4433
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xml	1652
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml	4429
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xml	4429
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xml	4429
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m03_regslice_0/cl_axi_interconnect_m03_regslice_0.xml	4429
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s00_regslice_0/cl_axi_interconnect_s00_regslice_0.xml	4443
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_s01_regslice_0/cl_axi_interconnect_s01_regslice_0.xml	4443
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_xbar_0/cl_axi_interconnect_xbar_0.xml	44007
hdk/common/shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml	4429
hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/bd_a493_xsdbm_0.xml	22275
hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_1/bd_a493_lut_buffer_0.xml	1019
hdk/common/shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.xml	890
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_0/bd_bf3f_microblaze_I_0.xml	27479
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_1/bd_bf3f_rst_0_0.xml	786
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_2/bd_bf3f_ilmb_0.xml	3476
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_3/bd_bf3f_dlmb_0.xml	3478
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_4/bd_bf3f_dlmb_cntlr_0.xml	4073
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_5/bd_bf3f_ilmb_cntlr_0.xml	4073
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_6/bd_bf3f_lmb_bram_I_0.xml	4240
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_7/bd_bf3f_second_dlmb_cntlr_0.xml	4073
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_8/bd_bf3f_second_ilmb_cntlr_0.xml	4073
hdk/common/shell_v04261818/design/ip/ddr4_core/bd_0/ip/ip_9/bd_bf3f_second_lmb_bram_I_0.xml	4240
hdk/common/shell_v04261818/design/ip/ddr4_core/ddr4_core.xml	9300
hdk/common/shell_v04261818/design/ip/ddr4_core/ip_0/ddr4_core_microblaze_mcs.xml	2331
hdk/common/shell_v04261818/design/ip/ddr4_core/ip_1/ddr4_core_phy.xml	5105
hdk/common/shell_v04261818/design/ip/dest_register_slice/dest_register_slice.xml	4406
hdk/common/shell_v04261818/design/ip/ila_0/ila_0.xml	74834
hdk/common/shell_v04261818/design/ip/ila_1/ila_1.xml	74847
hdk/common/shell_v04261818/design/ip/ila_vio_counter/ila_vio_counter.xml	74839
hdk/common/shell_v04261818/design/ip/src_register_slice/src_register_slice.xml	4406
hdk/common/shell_v04261818/design/ip/vio_0/vio_0.xml	20790
hdk/common/shell_v04261818/hlx/design/boards/board.xml	13
hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/component.xml	16542
hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/interface/aws_f1_sh1.xml	11
hdk/common/shell_v04261818/hlx/design/ip/aws_v1_0/interface/aws_f1_sh1_rtl.xml	2890
hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hello_world_ref/design.xml	10
hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_hls_dds/design.xml	10
hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/cl_ipi_cdma_test/design.xml	10
hdk/common/shell_v04261818/hlx/hlx_examples/build/IPI/hello_world/design.xml	10
hdk/common/shell_v04261818/hlx/hlx_examples/build/RTL/cl_dram_dma/design.xml	10
hdk/common/shell_v04261818/hlx/hlx_examples/build/RTL/cl_hello_world/design.xml	10
hdk/common/shell_v04261818/new_cl_template/build/README.md	118
hdk/common/verif/scripts/xilinx_task_pcie.patch	695
hdk/tests/HDK_TESTING.md	24
sdk/README.md	67
sdk/SDAccel/README.md	3
sdk/apps/virtual-ethernet/README.md	29
sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md	866
sdk/apps/virtual-ethernet/patches/pktgen-dpdk/master/0001-adjust-constants-for-the-ENA-driver.patch	22
sdk/apps/virtual-ethernet/patches/pktgen-dpdk/master/0002-print-warning-on-NUMA-socket-discrepancies.patch	28
sdk/apps/virtual-ethernet/patches/pktgen-dpdk/master/0003-remove-link-speed-status-probing-for-ENA.patch	27
sdk/apps/virtual-ethernet/patches/pktgen-dpdk/master/0004-make-jumbo-j-option-work-for-ENA.patch	23
sdk/apps/virtual-ethernet/patches/pktgen-dpdk/master/dpdk-0005-generate-igb-dpdk.patch	13
sdk/apps/virtual-ethernet/patches/spp-dpdk/master/0001-net-spp-initial-commit-of-AWS-SPP-network-driver.patch	3842
sdk/apps/virtual-ethernet/patches/spp-dpdk/master/0003-app-testpmd-tuned-for-single-mbuf-seg-jumbo-frames.patch	26
sdk/apps/virtual-ethernet/patches/spp-dpdk/master/0004-app-testpmd-added-spp-loop-to-fwd_engines.patch	510
sdk/apps/virtual-ethernet/patches/spp-dpdk/master/0005-app-testpmd-added-spp-eni-addr-swap-to-fwd_engines.patch	263
sdk/linux_kernel_drivers/README.md	2
sdk/linux_kernel_drivers/xdma/README.md	187
sdk/linux_kernel_drivers/xdma/user_defined_interrupts_README.md	65
sdk/linux_kernel_drivers/xdma/xdma_install.md	137
sdk/tests/SDK_TESTING.md	22
sdk/tests/fio_dma_tools/README.md	106
sdk/tests/fio_dma_tools/patches/fio-2.21/0001-filesetup-allow-FIO-to-work-with-F1-DMA-devices.patch	29
sdk/userspace/README.md	9
sdk/userspace/fpga_mgmt_tools/README.md	204
sdk/userspace/python_bindings/README.md	22
shared/tests/TESTING.md	80