in portable/NetworkInterface/xilinx_ultrascale/x_emacpsif_physpeed.c [1047:1374]
static void SetUpSLCRDivisors( u32 mac_baseaddr,
s32 speed )
{
volatile u32 slcrBaseAddress;
u32 SlcrDiv0 = 0;
u32 SlcrDiv1 = 0;
u32 SlcrTxClkCntrl;
u32 gigeversion;
volatile u32 CrlApbBaseAddr;
u32 CrlApbDiv0 = 0;
u32 CrlApbDiv1 = 0;
u32 CrlApbGemCtrl;
gigeversion = ( ( Xil_In32( mac_baseaddr + 0xFC ) ) >> 16 ) & 0xFFF;
if( gigeversion == 2 )
{
*( volatile u32 * ) ( SLCR_UNLOCK_ADDR ) = SLCR_UNLOCK_KEY_VALUE;
if( mac_baseaddr == ZYNQ_EMACPS_0_BASEADDR )
{
slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
}
else
{
slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
}
if( ( *( volatile u32 * ) ( UINTPTR ) ( slcrBaseAddress ) ) &
SLCR_GEM_SRCSEL_EMIO )
{
return;
}
if( speed == 1000 )
{
if( mac_baseaddr == XPAR_XEMACPS_0_BASEADDR )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
#endif
}
}
else if( speed == 100 )
{
if( mac_baseaddr == XPAR_XEMACPS_0_BASEADDR )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
#endif
}
}
else
{
if( mac_baseaddr == XPAR_XEMACPS_0_BASEADDR )
{
#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
#endif
}
else
{
#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
#endif
}
}
if( ( SlcrDiv0 != 0 ) && ( SlcrDiv1 != 0 ) )
{
SlcrTxClkCntrl = *( volatile u32 * ) ( UINTPTR ) ( slcrBaseAddress );
SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
*( volatile u32 * ) ( UINTPTR ) ( slcrBaseAddress ) = SlcrTxClkCntrl;
*( volatile u32 * ) ( SLCR_LOCK_ADDR ) = SLCR_LOCK_KEY_VALUE;
}
else
{
xil_printf( "Clock Divisors incorrect - Please check\n" );
}
}
else if( gigeversion == GEM_VERSION_ZYNQMP )
{
/* Setup divisors in CRL_APB for Zynq Ultrascale+ MPSoC */
if( mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR )
{
CrlApbBaseAddr = CRL_APB_GEM0_REF_CTRL;
}
else if( mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR )
{
CrlApbBaseAddr = CRL_APB_GEM1_REF_CTRL;
}
else if( mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR )
{
CrlApbBaseAddr = CRL_APB_GEM2_REF_CTRL;
}
else if( mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR )
{
CrlApbBaseAddr = CRL_APB_GEM3_REF_CTRL;
}
if( speed == 1000 )
{
if( mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1;
#endif
}
}
else if( speed == 100 )
{
if( mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1;
#endif
}
}
else
{
if( mac_baseaddr == ZYNQMP_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_2_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1;
#endif
}
else if( mac_baseaddr == ZYNQMP_EMACPS_3_BASEADDR )
{
#ifdef XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0;
CrlApbDiv1 = XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1;
#endif
}
}
if( ( CrlApbDiv0 != 0 ) && ( CrlApbDiv1 != 0 ) )
{
#if EL1_NONSECURE
XSmc_OutVar RegRead;
RegRead = Xil_Smc( MMIO_READ_SMC_FID, ( u64 ) ( CrlApbBaseAddr ),
0, 0, 0, 0, 0, 0 );
CrlApbGemCtrl = RegRead.Arg0 >> 32;
#else
CrlApbGemCtrl = *( volatile u32 * ) ( UINTPTR ) ( CrlApbBaseAddr );
#endif
CrlApbGemCtrl &= ~CRL_APB_GEM_DIV0_MASK;
CrlApbGemCtrl |= CrlApbDiv0 << CRL_APB_GEM_DIV0_SHIFT;
CrlApbGemCtrl &= ~CRL_APB_GEM_DIV1_MASK;
CrlApbGemCtrl |= CrlApbDiv1 << CRL_APB_GEM_DIV1_SHIFT;
#if EL1_NONSECURE
Xil_Smc( MMIO_WRITE_SMC_FID, ( u64 ) ( CrlApbBaseAddr ) | ( ( u64 ) ( 0xFFFFFFFF ) << 32 ),
( u64 ) CrlApbGemCtrl, 0, 0, 0, 0, 0 );
do
{
RegRead = Xil_Smc( MMIO_READ_SMC_FID, ( u64 ) ( CrlApbBaseAddr ),
0, 0, 0, 0, 0, 0 );
} while( ( RegRead.Arg0 >> 32 ) != CrlApbGemCtrl );
#else
*( volatile u32 * ) ( UINTPTR ) ( CrlApbBaseAddr ) = CrlApbGemCtrl;
#endif
}
else
{
xil_printf( "Clock Divisors incorrect - Please check\n" );
}
}
else if( gigeversion == GEM_VERSION_VERSAL )
{
/* Setup divisors in CRL for Versal */
if( mac_baseaddr == VERSAL_EMACPS_0_BASEADDR )
{
CrlApbBaseAddr = VERSAL_CRL_GEM0_REF_CTRL;
#if EL1_NONSECURE
ClkId = CLK_GEM0_REF;
#endif
}
else if( mac_baseaddr == VERSAL_EMACPS_1_BASEADDR )
{
CrlApbBaseAddr = VERSAL_CRL_GEM1_REF_CTRL;
#if EL1_NONSECURE
ClkId = CLK_GEM1_REF;
#endif
}
if( speed == 1000 )
{
if( mac_baseaddr == VERSAL_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
#endif
}
else if( mac_baseaddr == VERSAL_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
#endif
}
}
else if( speed == 100 )
{
if( mac_baseaddr == VERSAL_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
#endif
}
else if( mac_baseaddr == VERSAL_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
#endif
}
}
else
{
if( mac_baseaddr == VERSAL_EMACPS_0_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
#endif
}
else if( mac_baseaddr == VERSAL_EMACPS_1_BASEADDR )
{
#ifdef XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
CrlApbDiv0 = XPAR_PSV_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
#endif
}
}
if( CrlApbDiv0 != 0 )
{
#if EL1_NONSECURE
Xil_Smc( PM_SET_DIVIDER_SMC_FID, ( ( ( u64 ) CrlApbDiv0 << 32 ) | ClkId ), 0, 0, 0, 0, 0, 0 );
#else
CrlApbGemCtrl = Xil_In32( ( UINTPTR ) CrlApbBaseAddr );
CrlApbGemCtrl &= ~VERSAL_CRL_GEM_DIV_MASK;
CrlApbGemCtrl |= CrlApbDiv0 << VERSAL_CRL_APB_GEM_DIV_SHIFT;
Xil_Out32( ( UINTPTR ) CrlApbBaseAddr, CrlApbGemCtrl );
#endif
}
else
{
xil_printf( "Clock Divisors incorrect - Please check\n" );
}
}
}