in boards/STM32L475_Discovery/STM32L4xx_HAL_Driver/stm32l4xx_hal_rcc_ex.c [922:1683]
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
uint32_t frequency = 0U;
uint32_t srcclk = 0U;
uint32_t pllvco = 0U, plln = 0U, pllp = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
if(PeriphClk == RCC_PERIPHCLK_RTC)
{
/* Get the current RTC source */
srcclk = __HAL_RCC_GET_RTC_SOURCE();
/* Check if LSE is ready and if RTC clock selection is LSE */
if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Check if LSI is ready and if RTC clock selection is LSI */
else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
{
frequency = LSI_VALUE;
}
/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
{
frequency = HSE_VALUE / 32;
}
/* Clock not enabled for RTC*/
else
{
frequency = 0U;
}
}
else
{
/* Other external peripheral clock source than RTC */
/* Compute PLL clock input */
if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
{
/*MSI frequency range in HZ*/
pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
}
else
{
pllvco = 0U;
}
}
else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
pllvco = HSI_VALUE;
}
else
{
pllvco = 0U;
}
}
else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
{
pllvco = HSE_VALUE;
}
else
{
pllvco = 0U;
}
}
else /* No source */
{
pllvco = 0U;
}
/* f(PLL Source) / PLLM */
pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
switch(PeriphClk)
{
#if defined(SAI2)
case RCC_PERIPHCLK_SAI1:
case RCC_PERIPHCLK_SAI2:
if(PeriphClk == RCC_PERIPHCLK_SAI1)
{
srcclk = __HAL_RCC_GET_SAI1_SOURCE();
if(srcclk == RCC_SAI1CLKSOURCE_PIN)
{
frequency = EXTERNAL_SAI1_CLOCK_VALUE;
}
/* Else, PLL clock output to check below */
}
else /* RCC_PERIPHCLK_SAI2 */
{
srcclk = __HAL_RCC_GET_SAI2_SOURCE();
if(srcclk == RCC_SAI2CLKSOURCE_PIN)
{
frequency = EXTERNAL_SAI2_CLOCK_VALUE;
}
/* Else, PLL clock output to check below */
}
#else
case RCC_PERIPHCLK_SAI1:
if(PeriphClk == RCC_PERIPHCLK_SAI1)
{
srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL);
if(srcclk == RCC_SAI1CLKSOURCE_PIN)
{
frequency = EXTERNAL_SAI1_CLOCK_VALUE;
}
/* Else, PLL clock output to check below */
}
#endif /* SAI2 */
if(frequency == 0U)
{
#if defined(SAI2)
if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL))
{
if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
{
/* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */
{
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
{
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
#else
if(srcclk == RCC_SAI1CLKSOURCE_PLL)
{
if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET)
{
/* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
/* HSI automatically selected as clock source if PLLs not enabled */
frequency = HSI_VALUE;
}
else
{
/* No clock source */
frequency = 0U;
}
}
else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1)
{
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
{
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
#endif
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
{
/* HSI automatically selected as clock source if PLLs not enabled */
frequency = HSI_VALUE;
}
else
{
/* No clock source */
frequency = 0U;
}
}
#endif /* SAI2 */
#if defined(RCC_PLLSAI2_SUPPORT)
else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2))
{
if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
{
/* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
{
pllp = 17U;
}
else
{
pllp = 7U;
}
}
frequency = (pllvco * plln) / pllp;
}
}
#endif /* RCC_PLLSAI2_SUPPORT */
else
{
/* No clock source */
frequency = 0U;
}
}
break;
#if defined(USB_OTG_FS) || defined(USB)
case RCC_PERIPHCLK_USB:
#endif /* USB_OTG_FS || USB */
case RCC_PERIPHCLK_RNG:
#if defined(SDMMC1)
case RCC_PERIPHCLK_SDMMC1:
#endif /* SDMMC1 */
srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL);
if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))
{
/*MSI frequency range in HZ*/
frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)];
}
else
{
frequency = 0U;
}
}
else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
{
/* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
}
else
{
frequency = 0U;
}
}
else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */
{
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
{
/* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
}
else
{
frequency = 0U;
}
}
#if defined(RCC_HSI48_SUPPORT)
else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */
{
frequency = HSI48_VALUE;
}
else /* No clock source */
{
frequency = 0U;
}
#else
else /* No clock source */
{
frequency = 0U;
}
#endif /* RCC_HSI48_SUPPORT */
break;
case RCC_PERIPHCLK_USART1:
/* Get the current USART1 source */
srcclk = __HAL_RCC_GET_USART1_SOURCE();
if(srcclk == RCC_USART1CLKSOURCE_PCLK2)
{
frequency = HAL_RCC_GetPCLK2Freq();
}
else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for USART1 */
else
{
frequency = 0U;
}
break;
case RCC_PERIPHCLK_USART2:
/* Get the current USART2 source */
srcclk = __HAL_RCC_GET_USART2_SOURCE();
if(srcclk == RCC_USART2CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for USART2 */
else
{
frequency = 0U;
}
break;
#if defined(USART3)
case RCC_PERIPHCLK_USART3:
/* Get the current USART3 source */
srcclk = __HAL_RCC_GET_USART3_SOURCE();
if(srcclk == RCC_USART3CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for USART3 */
else
{
frequency = 0U;
}
break;
#endif /* USART3 */
#if defined(UART4)
case RCC_PERIPHCLK_UART4:
/* Get the current UART4 source */
srcclk = __HAL_RCC_GET_UART4_SOURCE();
if(srcclk == RCC_UART4CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for UART4 */
else
{
frequency = 0U;
}
break;
#endif /* UART4 */
#if defined(UART5)
case RCC_PERIPHCLK_UART5:
/* Get the current UART5 source */
srcclk = __HAL_RCC_GET_UART5_SOURCE();
if(srcclk == RCC_UART5CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for UART5 */
else
{
frequency = 0U;
}
break;
#endif /* UART5 */
case RCC_PERIPHCLK_LPUART1:
/* Get the current LPUART1 source */
srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for LPUART1 */
else
{
frequency = 0U;
}
break;
case RCC_PERIPHCLK_ADC:
srcclk = __HAL_RCC_GET_ADC_SOURCE();
if(srcclk == RCC_ADCCLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1)
{
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
{
/* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
}
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2)
{
if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
{
/* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
}
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
/* Clock not enabled for ADC */
else
{
frequency = 0U;
}
break;
#if defined(DFSDM1_Filter0)
case RCC_PERIPHCLK_DFSDM1:
/* Get the current DFSDM1 source */
srcclk = __HAL_RCC_GET_DFSDM1_SOURCE();
if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2)
{
frequency = HAL_RCC_GetPCLK2Freq();
}
else
{
frequency = HAL_RCC_GetSysClockFreq();
}
break;
#endif /* DFSDM1_Filter0 */
case RCC_PERIPHCLK_I2C1:
/* Get the current I2C1 source */
srcclk = __HAL_RCC_GET_I2C1_SOURCE();
if(srcclk == RCC_I2C1CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
/* Clock not enabled for I2C1 */
else
{
frequency = 0U;
}
break;
#if defined(I2C2)
case RCC_PERIPHCLK_I2C2:
/* Get the current I2C2 source */
srcclk = __HAL_RCC_GET_I2C2_SOURCE();
if(srcclk == RCC_I2C2CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
/* Clock not enabled for I2C2 */
else
{
frequency = 0U;
}
break;
#endif /* I2C2 */
case RCC_PERIPHCLK_I2C3:
/* Get the current I2C3 source */
srcclk = __HAL_RCC_GET_I2C3_SOURCE();
if(srcclk == RCC_I2C3CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
/* Clock not enabled for I2C3 */
else
{
frequency = 0U;
}
break;
#if defined(I2C4)
case RCC_PERIPHCLK_I2C4:
/* Get the current I2C4 source */
srcclk = __HAL_RCC_GET_I2C4_SOURCE();
if(srcclk == RCC_I2C4CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
{
frequency = HAL_RCC_GetSysClockFreq();
}
else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
/* Clock not enabled for I2C4 */
else
{
frequency = 0U;
}
break;
#endif /* I2C4 */
case RCC_PERIPHCLK_LPTIM1:
/* Get the current LPTIM1 source */
srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
{
frequency = LSI_VALUE;
}
else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for LPTIM1 */
else
{
frequency = 0U;
}
break;
case RCC_PERIPHCLK_LPTIM2:
/* Get the current LPTIM2 source */
srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
{
frequency = LSI_VALUE;
}
else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
{
frequency = LSE_VALUE;
}
/* Clock not enabled for LPTIM2 */
else
{
frequency = 0U;
}
break;
#if defined(SWPMI1)
case RCC_PERIPHCLK_SWPMI1:
/* Get the current SWPMI1 source */
srcclk = __HAL_RCC_GET_SWPMI1_SOURCE();
if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1)
{
frequency = HAL_RCC_GetPCLK1Freq();
}
else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
{
frequency = HSI_VALUE;
}
/* Clock not enabled for SWPMI1 */
else
{
frequency = 0U;
}
break;
#endif /* SWPMI1 */
default:
break;
}
}
return(frequency);
}