IRAM_ATTR static int map_rom_segments()

in proj/espressif/esp32/app/main/start.c [249:303]

• 38 lines of code
• 2 McCabe index (conditional complexity)

IRAM_ATTR static int map_rom_segments( void )
{
    uint32_t rc = ESP_OK;

    /* Cache ROM segments into cache */
    volatile uint32_t irom_lma = (uint32_t)&_image_irom_lma;
    volatile uint32_t irom_vma = (uint32_t)&_image_irom_vma;
    volatile uint32_t irom_size = (uint32_t)&_image_irom_size;

    volatile uint32_t drom_lma = (uint32_t)&_image_drom_lma;
    volatile uint32_t drom_vma = (uint32_t)&_image_drom_vma;
    volatile uint32_t drom_size = (uint32_t)&_image_drom_size;

    volatile uint32_t irom_abs_lma = CONFIG_ESP_APPLICATION_PRIMARY_START_ADDRESS + irom_lma;
    volatile uint32_t irom_abs_vma = irom_vma;
    
    volatile uint32_t drom_abs_lma = CONFIG_ESP_APPLICATION_PRIMARY_START_ADDRESS + drom_lma;
    volatile uint32_t drom_abs_vma = drom_vma;

    /* Disable and flush PRO CPU cache */
    Cache_Read_Disable(0);
    Cache_Flush(0);

    /* Invalidate MMU entries, for fresh start with app */
    for(int i=0; i<DPORT_FLASH_MMU_TABLE_SIZE; i++)
    {
        DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL;
    }

    /* Verify alignment reqired for MMU */
    uint32_t drom_aligned_lma = drom_abs_lma & MMU_FLASH_MASK;
    uint32_t drom_aligned_vma = drom_abs_vma & MMU_FLASH_MASK;
    uint32_t drom_page_count = count_mmu_pages( drom_size, drom_aligned_vma );
    rc |= cache_flash_mmu_set(0, 0, drom_aligned_vma, drom_aligned_lma, 64, drom_page_count);
    rc |= cache_flash_mmu_set(1, 0, drom_aligned_vma, drom_aligned_lma, 64, drom_page_count);

    uint32_t irom_aligned_lma = irom_abs_lma & MMU_FLASH_MASK;
    uint32_t irom_aligned_vma = irom_abs_vma & MMU_FLASH_MASK;
    uint32_t irom_page_count = count_mmu_pages( irom_size, irom_aligned_vma );
    rc |= cache_flash_mmu_set(0, 0, irom_aligned_vma, irom_aligned_lma, 64, irom_page_count);
    rc |= cache_flash_mmu_set(1, 0, irom_aligned_vma, irom_aligned_lma, 64, irom_page_count);

    DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, ( DPORT_PRO_CACHE_MASK_IRAM0 | 
                                                    DPORT_PRO_CACHE_MASK_DROM0 | 
                                                    DPORT_PRO_CACHE_MASK_DRAM1 ));

    DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, ( DPORT_APP_CACHE_MASK_IRAM0 | 
                                                    DPORT_APP_CACHE_MASK_DROM0 | 
                                                    DPORT_APP_CACHE_MASK_DRAM1 ));


    Cache_Read_Enable(0);

    return rc;
}