in Drivers/STM32U5xx_HAL/Src/stm32u5xx_hal_rcc_ex.c [348:974]
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
{
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
HAL_StatusTypeDef status = HAL_OK; /* Final status */
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
/*-------------------------- USART1 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
}
/*-------------------------- USART2 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
}
/*-------------------------- USART3 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
}
/*-------------------------- UART4 clock source configuration --------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
}
/*-------------------------- UART5 clock source configuration --------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
}
/*-------------------------- LPUART1 clock source configuration ------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
}
/*-------------------------- I2C3 clock source configuration ---------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
}
/*-------------------------- I2C4 clock source configuration ---------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
}
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
{
assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
}
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
{
assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
}
/*-------------------------- LPTIM34 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34))
{
assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection));
__HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection);
}
/*-------------------------- SAI1 clock source configuration ---------------------*/
if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
switch (pPeriphClkInit->Sai1ClockSelection)
{
case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/
/* Enable SAI Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
/* SAI1 clock source config set later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
/* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
/* SAI1 clock source config set later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
/* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
/* SAI1 clock source config set later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
/* SAI1 clock source configuration done later after clock selection check */
break;
case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
/* SAI1 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI1 clock*/
__HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- SAI2 clock source configuration ---------------------*/
if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
switch (pPeriphClkInit->Sai2ClockSelection)
{
case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/
/* Enable SAI Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
/* SAI2 clock source config set later after clock selection check */
break;
case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
/* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
/* SAI2 clock source config set later after clock selection check */
break;
case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
/* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
/* SAI2 clock source config set later after clock selection check */
break;
case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
/* SAI2 clock source configuration done later after clock selection check */
break;
case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
/* SAI2 clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of SAI2 clock*/
__HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- ADCDAC clock source configuration ----------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
{
/* Check the parameters */
assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
switch (pPeriphClkInit->AdcDacClockSelection)
{
case RCC_ADCDACCLKSOURCE_PLL2:
/* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
break;
case RCC_ADCDACCLKSOURCE_SYSCLK:
case RCC_ADCDACCLKSOURCE_HCLK:
case RCC_ADCDACCLKSOURCE_HSE:
case RCC_ADCDACCLKSOURCE_HSI:
case RCC_ADCDACCLKSOURCE_MSIK:
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Configure the ADC1 interface clock source */
__HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- MDF1 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
{
/* Check the parameters */
assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection));
switch (pPeriphClkInit->Mdf1ClockSelection)
{
case RCC_MDF1CLKSOURCE_PLL1:
/* Enable PLL1 Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
break;
case RCC_MDF1CLKSOURCE_PLL3:
/* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
break;
case RCC_MDF1CLKSOURCE_HCLK:
break;
case RCC_MDF1CLKSOURCE_PIN:
break;
case RCC_MDF1CLKSOURCE_MSIK:
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Configure the MDF1 interface clock source */
__HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- ADF1 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
{
/* Check the parameters */
assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
switch (pPeriphClkInit->Adf1ClockSelection)
{
case RCC_ADF1CLKSOURCE_PLL1:
/* Enable PLL1 Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
break;
case RCC_ADF1CLKSOURCE_PLL3:
/* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
break;
case RCC_ADF1CLKSOURCE_HCLK:
break;
case RCC_ADF1CLKSOURCE_PIN:
break;
case RCC_ADF1CLKSOURCE_MSIK:
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Configure the ADF1 interface clock source */
__HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- RTC clock source configuration ----------------------*/
if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
{
FlagStatus pwrclkchanged = RESET;
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
/* Enable write access to Backup domain */
SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
ret = HAL_TIMEOUT;
break;
}
}
if (ret == HAL_OK)
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
{
ret = HAL_TIMEOUT;
break;
}
}
}
if (ret == HAL_OK)
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
else
{
/* set overall return value */
status = ret;
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(pPeriphClkInit->Clk48ClockSelection));
switch (pPeriphClkInit->Clk48ClockSelection)
{
case RCC_CLK48CLKSOURCE_PLL2:
/* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
break;
case RCC_CLK48CLKSOURCE_PLL1:
/* Enable CLK48 Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
break;
case RCC_CLK48CLKSOURCE_HSI48:
break;
case RCC_CLK48CLKSOURCE_MSIK:
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(pPeriphClkInit->Clk48ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*------------------------------ RNG Configuration -------------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
{
/* Check the parameters */
assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
switch (pPeriphClkInit->RngClockSelection)
{
case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/
/* RNG clock source configuration done later after clock selection check */
break;
case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/
/* RNG clock source configuration done later after clock selection check */
break;
case RCC_RNGCLKSOURCE_HSI48:
/* HSI48 oscillator is used as source of RNG clock */
/* RNG clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of RNG clock*/
__HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- SAES clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
{
/* Check the parameters */
assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection));
/* Configure the SAES clock source */
__HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
}
/*-------------------------- SDMMC1/2 clock source configuration -------------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
{
/* Check the parameters */
assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection));
if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1)
{
/* Enable PLL1 P CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
}
/* Configure the SDMMC1/2 clock source */
__HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection);
}
/*-------------------------- SPI1 clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
{
/* Check the parameters */
assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
/* Configure the SPI1 clock source */
__HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
}
/*-------------------------- SPI2 clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
{
/* Check the parameters */
assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
/* Configure the SPI2 clock source */
__HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
}
/*-------------------------- SPI3 clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
{
/* Check the parameters */
assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
/* Configure the SPI3 clock source */
__HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
}
/*-------------------------- OctoSPIx clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
{
/* Check the parameters */
assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1)
{
/* Enable PLL1 Q CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
}
if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
{
/* Enable PLL2 Q CLK output */
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
}
/* Configure the OctoSPI clock source */
__HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
}
/*-------------------------- FDCAN1 kernel clock source configuration -------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
{
assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
switch (pPeriphClkInit->Fdcan1ClockSelection)
{
case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
/* FDCAN1 kernel clock source config set later after clock selection check */
break;
case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
/* Enable 48M2 Clock output generated from System PLL */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
/* FDCAN1 kernel clock source config set later after clock selection check */
break;
case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
/* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
/* FDCAN1 kernel clock source config set later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if (ret == HAL_OK)
{
/* Set the source of FDCAN1 kernel clock*/
__HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
/*-------------------------- DAC1 clock source configuration ----------------*/
if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
{
/* Check the parameters */
assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
/* Configure the DAC1 clock source */
__HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
}
return status;
}