in arch/risc-v/src/mpfs/mpfs_ddr.c [814:1574]
static void mpfs_init_ddrc(void)
{
/* Turn on DDRC clock */
modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
SYSREG_SUBBLK_CLOCK_CR_DDRC);
/* Remove soft reset */
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0,
SYSREG_SUBBLK_CLOCK_CR_DDRC);
modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
SYSREG_SUBBLK_CLOCK_CR_DDRC, 0);
putreg32(LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP,
MPFS_DDR_CSR_APB_CFG_MANUAL_ADDRESS_MAP);
putreg32(LIBERO_SETTING_CFG_CHIPADDR_MAP,
MPFS_DDR_CSR_APB_CFG_CHIPADDR_MAP);
putreg32(LIBERO_SETTING_CFG_CIDADDR_MAP,
MPFS_DDR_CSR_APB_CFG_CIDADDR_MAP);
putreg32(LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW,
MPFS_DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_LOW);
putreg32(LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH,
MPFS_DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH);
putreg32(LIBERO_SETTING_CFG_BANKADDR_MAP_0,
MPFS_DDR_CSR_APB_CFG_BANKADDR_MAP_0);
putreg32(LIBERO_SETTING_CFG_BANKADDR_MAP_1,
MPFS_DDR_CSR_APB_CFG_BANKADDR_MAP_1);
putreg32(LIBERO_SETTING_CFG_ROWADDR_MAP_0,
MPFS_DDR_CSR_APB_CFG_ROWADDR_MAP_0);
putreg32(LIBERO_SETTING_CFG_ROWADDR_MAP_1,
MPFS_DDR_CSR_APB_CFG_ROWADDR_MAP_1);
putreg32(LIBERO_SETTING_CFG_ROWADDR_MAP_2,
MPFS_DDR_CSR_APB_CFG_ROWADDR_MAP_2);
putreg32(LIBERO_SETTING_CFG_ROWADDR_MAP_3,
MPFS_DDR_CSR_APB_CFG_ROWADDR_MAP_3);
putreg32(LIBERO_SETTING_CFG_COLADDR_MAP_0,
MPFS_DDR_CSR_APB_CFG_COLADDR_MAP_0);
putreg32(LIBERO_SETTING_CFG_COLADDR_MAP_1,
MPFS_DDR_CSR_APB_CFG_COLADDR_MAP_1);
putreg32(LIBERO_SETTING_CFG_COLADDR_MAP_2,
MPFS_DDR_CSR_APB_CFG_COLADDR_MAP_2);
putreg32(LIBERO_SETTING_CFG_VRCG_ENABLE,
MPFS_DDR_CSR_APB_CFG_VRCG_ENABLE);
putreg32(LIBERO_SETTING_CFG_VRCG_DISABLE,
MPFS_DDR_CSR_APB_CFG_VRCG_DISABLE);
putreg32(LIBERO_SETTING_CFG_WRITE_LATENCY_SET,
MPFS_DDR_CSR_APB_CFG_WRITE_LATENCY_SET);
putreg32(LIBERO_SETTING_CFG_THERMAL_OFFSET,
MPFS_DDR_CSR_APB_CFG_THERMAL_OFFSET);
putreg32(LIBERO_SETTING_CFG_SOC_ODT,
MPFS_DDR_CSR_APB_CFG_SOC_ODT);
putreg32(LIBERO_SETTING_CFG_ODTE_CK,
MPFS_DDR_CSR_APB_CFG_ODTE_CK);
putreg32(LIBERO_SETTING_CFG_ODTE_CS,
MPFS_DDR_CSR_APB_CFG_ODTE_CS);
putreg32(LIBERO_SETTING_CFG_ODTD_CA,
MPFS_DDR_CSR_APB_CFG_ODTD_CA);
putreg32(LIBERO_SETTING_CFG_LPDDR4_FSP_OP,
MPFS_DDR_CSR_APB_CFG_LPDDR4_FSP_OP);
putreg32(LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX,
MPFS_DDR_CSR_APB_CFG_GENERATE_REFRESH_ON_SRX);
putreg32(LIBERO_SETTING_CFG_DBI_CL,
MPFS_DDR_CSR_APB_CFG_DBI_CL);
putreg32(LIBERO_SETTING_CFG_NON_DBI_CL,
MPFS_DDR_CSR_APB_CFG_NON_DBI_CL);
putreg32(LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0,
MPFS_DDR_CSR_APB_INIT_FORCE_WRITE_DATA_0);
putreg32(LIBERO_SETTING_CFG_WRITE_CRC,
MPFS_DDR_CSR_APB_CFG_WRITE_CRC);
putreg32(LIBERO_SETTING_CFG_MPR_READ_FORMAT,
MPFS_DDR_CSR_APB_CFG_MPR_READ_FORMAT);
putreg32(LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM,
MPFS_DDR_CSR_APB_CFG_WR_CMD_LAT_CRC_DM);
putreg32(LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE,
MPFS_DDR_CSR_APB_CFG_FINE_GRAN_REF_MODE);
putreg32(LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT,
MPFS_DDR_CSR_APB_CFG_TEMP_SENSOR_READOUT);
putreg32(LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN,
MPFS_DDR_CSR_APB_CFG_PER_DRAM_ADDR_EN);
putreg32(LIBERO_SETTING_CFG_GEARDOWN_MODE,
MPFS_DDR_CSR_APB_CFG_GEARDOWN_MODE);
putreg32(LIBERO_SETTING_CFG_WR_PREAMBLE,
MPFS_DDR_CSR_APB_CFG_WR_PREAMBLE);
putreg32(LIBERO_SETTING_CFG_RD_PREAMBLE,
MPFS_DDR_CSR_APB_CFG_RD_PREAMBLE);
putreg32(LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE,
MPFS_DDR_CSR_APB_CFG_RD_PREAMB_TRN_MODE);
putreg32(LIBERO_SETTING_CFG_SR_ABORT,
MPFS_DDR_CSR_APB_CFG_SR_ABORT);
putreg32(LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY,
MPFS_DDR_CSR_APB_CFG_CS_TO_CMDADDR_LATENCY);
putreg32(LIBERO_SETTING_CFG_INT_VREF_MON,
MPFS_DDR_CSR_APB_CFG_INT_VREF_MON);
putreg32(LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE,
MPFS_DDR_CSR_APB_CFG_TEMP_CTRL_REF_MODE);
putreg32(LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE,
MPFS_DDR_CSR_APB_CFG_TEMP_CTRL_REF_RANGE);
putreg32(LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE,
MPFS_DDR_CSR_APB_CFG_MAX_PWR_DOWN_MODE);
putreg32(LIBERO_SETTING_CFG_READ_DBI,
MPFS_DDR_CSR_APB_CFG_READ_DBI);
putreg32(LIBERO_SETTING_CFG_WRITE_DBI,
MPFS_DDR_CSR_APB_CFG_WRITE_DBI);
putreg32(LIBERO_SETTING_CFG_DATA_MASK,
MPFS_DDR_CSR_APB_CFG_DATA_MASK);
putreg32(LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR,
MPFS_DDR_CSR_APB_CFG_CA_PARITY_PERSIST_ERR);
putreg32(LIBERO_SETTING_CFG_RTT_PARK,
MPFS_DDR_CSR_APB_CFG_RTT_PARK);
putreg32(LIBERO_SETTING_CFG_ODT_INBUF_4_PD,
MPFS_DDR_CSR_APB_CFG_ODT_INBUF_4_PD);
putreg32(LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS,
MPFS_DDR_CSR_APB_CFG_CA_PARITY_ERR_STATUS);
putreg32(LIBERO_SETTING_CFG_CRC_ERROR_CLEAR,
MPFS_DDR_CSR_APB_CFG_CRC_ERROR_CLEAR);
putreg32(LIBERO_SETTING_CFG_CA_PARITY_LATENCY,
MPFS_DDR_CSR_APB_CFG_CA_PARITY_LATENCY);
putreg32(LIBERO_SETTING_CFG_CCD_S,
MPFS_DDR_CSR_APB_CFG_CCD_S);
putreg32(LIBERO_SETTING_CFG_CCD_L,
MPFS_DDR_CSR_APB_CFG_CCD_L);
putreg32(LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE,
MPFS_DDR_CSR_APB_CFG_VREFDQ_TRN_ENABLE);
putreg32(LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE,
MPFS_DDR_CSR_APB_CFG_VREFDQ_TRN_RANGE);
putreg32(LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE,
MPFS_DDR_CSR_APB_CFG_VREFDQ_TRN_VALUE);
putreg32(LIBERO_SETTING_CFG_RRD_S, MPFS_DDR_CSR_APB_CFG_RRD_S);
putreg32(LIBERO_SETTING_CFG_RRD_L, MPFS_DDR_CSR_APB_CFG_RRD_L);
putreg32(LIBERO_SETTING_CFG_WTR_S, MPFS_DDR_CSR_APB_CFG_WTR_S);
putreg32(LIBERO_SETTING_CFG_WTR_L, MPFS_DDR_CSR_APB_CFG_WTR_L);
putreg32(LIBERO_SETTING_CFG_WTR_S_CRC_DM,
MPFS_DDR_CSR_APB_CFG_WTR_S_CRC_DM);
putreg32(LIBERO_SETTING_CFG_WTR_L_CRC_DM,
MPFS_DDR_CSR_APB_CFG_WTR_L_CRC_DM);
putreg32(LIBERO_SETTING_CFG_WR_CRC_DM, MPFS_DDR_CSR_APB_CFG_WR_CRC_DM);
putreg32(LIBERO_SETTING_CFG_RFC1, MPFS_DDR_CSR_APB_CFG_RFC1);
putreg32(LIBERO_SETTING_CFG_RFC2, MPFS_DDR_CSR_APB_CFG_RFC2);
putreg32(LIBERO_SETTING_CFG_RFC4, MPFS_DDR_CSR_APB_CFG_RFC4);
putreg32(LIBERO_SETTING_CFG_NIBBLE_DEVICES,
MPFS_DDR_CSR_APB_CFG_NIBBLE_DEVICES);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_1);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_0);
putreg32(LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1,
MPFS_DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_1);
putreg32(LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS,
MPFS_DDR_CSR_APB_CFG_NUM_LOGICAL_RANKS_PER_3DS);
putreg32(LIBERO_SETTING_CFG_RFC_DLR1, MPFS_DDR_CSR_APB_CFG_RFC_DLR1);
putreg32(LIBERO_SETTING_CFG_RFC_DLR2, MPFS_DDR_CSR_APB_CFG_RFC_DLR2);
putreg32(LIBERO_SETTING_CFG_RFC_DLR4, MPFS_DDR_CSR_APB_CFG_RFC_DLR4);
putreg32(LIBERO_SETTING_CFG_RRD_DLR, MPFS_DDR_CSR_APB_CFG_RRD_DLR);
putreg32(LIBERO_SETTING_CFG_FAW_DLR, MPFS_DDR_CSR_APB_CFG_FAW_DLR);
putreg32(LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY,
MPFS_DDR_CSR_APB_CFG_ADVANCE_ACTIVATE_READY);
putreg32(LIBERO_SETTING_CTRLR_SOFT_RESET_N,
MPFS_DDR_CSR_APB_CTRLR_SOFT_RESET_N);
putreg32(LIBERO_SETTING_CFG_LOOKAHEAD_PCH,
MPFS_DDR_CSR_APB_CFG_LOOKAHEAD_PCH);
putreg32(LIBERO_SETTING_CFG_LOOKAHEAD_ACT,
MPFS_DDR_CSR_APB_CFG_LOOKAHEAD_ACT);
putreg32(LIBERO_SETTING_INIT_AUTOINIT_DISABLE,
MPFS_DDR_CSR_APB_INIT_AUTOINIT_DISABLE);
putreg32(LIBERO_SETTING_INIT_FORCE_RESET,
MPFS_DDR_CSR_APB_INIT_FORCE_RESET);
putreg32(LIBERO_SETTING_INIT_GEARDOWN_EN,
MPFS_DDR_CSR_APB_INIT_GEARDOWN_EN);
putreg32(LIBERO_SETTING_INIT_DISABLE_CKE,
MPFS_DDR_CSR_APB_INIT_DISABLE_CKE);
putreg32(LIBERO_SETTING_INIT_CS,
MPFS_DDR_CSR_APB_INIT_CS);
putreg32(LIBERO_SETTING_INIT_PRECHARGE_ALL,
MPFS_DDR_CSR_APB_INIT_PRECHARGE_ALL);
putreg32(LIBERO_SETTING_INIT_REFRESH, MPFS_DDR_CSR_APB_INIT_REFRESH);
putreg32(LIBERO_SETTING_INIT_ZQ_CAL_REQ, MPFS_DDR_CSR_APB_INIT_ZQ_CAL_REQ);
putreg32(LIBERO_SETTING_CFG_BL, MPFS_DDR_CSR_APB_CFG_BL);
putreg32(LIBERO_SETTING_CTRLR_INIT, MPFS_DDR_CSR_APB_CTRLR_INIT);
putreg32(LIBERO_SETTING_CFG_AUTO_REF_EN, MPFS_DDR_CSR_APB_CFG_AUTO_REF_EN);
putreg32(LIBERO_SETTING_CFG_RAS, MPFS_DDR_CSR_APB_CFG_RAS);
putreg32(LIBERO_SETTING_CFG_RCD, MPFS_DDR_CSR_APB_CFG_RCD);
putreg32(LIBERO_SETTING_CFG_RRD, MPFS_DDR_CSR_APB_CFG_RRD);
putreg32(LIBERO_SETTING_CFG_RP, MPFS_DDR_CSR_APB_CFG_RP);
putreg32(LIBERO_SETTING_CFG_RC, MPFS_DDR_CSR_APB_CFG_RC);
putreg32(LIBERO_SETTING_CFG_FAW, MPFS_DDR_CSR_APB_CFG_FAW);
putreg32(LIBERO_SETTING_CFG_RFC, MPFS_DDR_CSR_APB_CFG_RFC);
putreg32(LIBERO_SETTING_CFG_RTP, MPFS_DDR_CSR_APB_CFG_RTP);
putreg32(LIBERO_SETTING_CFG_WR, MPFS_DDR_CSR_APB_CFG_WR);
putreg32(LIBERO_SETTING_CFG_WTR, MPFS_DDR_CSR_APB_CFG_WTR);
putreg32(LIBERO_SETTING_CFG_PASR, MPFS_DDR_CSR_APB_CFG_PASR);
putreg32(LIBERO_SETTING_CFG_XP, MPFS_DDR_CSR_APB_CFG_XP);
putreg32(LIBERO_SETTING_CFG_XSR, MPFS_DDR_CSR_APB_CFG_XSR);
putreg32(LIBERO_SETTING_CFG_CL, MPFS_DDR_CSR_APB_CFG_CL);
putreg32(LIBERO_SETTING_CFG_READ_TO_WRITE,
MPFS_DDR_CSR_APB_CFG_READ_TO_WRITE);
putreg32(LIBERO_SETTING_CFG_WRITE_TO_WRITE,
MPFS_DDR_CSR_APB_CFG_WRITE_TO_WRITE);
putreg32(LIBERO_SETTING_CFG_WRITE_TO_WRITE,
MPFS_DDR_CSR_APB_CFG_READ_TO_READ);
putreg32(LIBERO_SETTING_CFG_WRITE_TO_WRITE,
MPFS_DDR_CSR_APB_CFG_WRITE_TO_READ);
putreg32(LIBERO_SETTING_CFG_READ_TO_WRITE_ODT,
MPFS_DDR_CSR_APB_CFG_READ_TO_WRITE_ODT);
putreg32(LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT,
MPFS_DDR_CSR_APB_CFG_WRITE_TO_WRITE_ODT);
putreg32(LIBERO_SETTING_CFG_READ_TO_READ_ODT,
MPFS_DDR_CSR_APB_CFG_READ_TO_READ_ODT);
putreg32(LIBERO_SETTING_CFG_WRITE_TO_READ_ODT,
MPFS_DDR_CSR_APB_CFG_WRITE_TO_READ_ODT);
putreg32(LIBERO_SETTING_CFG_MIN_READ_IDLE,
MPFS_DDR_CSR_APB_CFG_MIN_READ_IDLE);
putreg32(LIBERO_SETTING_CFG_MRD, MPFS_DDR_CSR_APB_CFG_MRD);
putreg32(LIBERO_SETTING_CFG_BT, MPFS_DDR_CSR_APB_CFG_BT);
putreg32(LIBERO_SETTING_CFG_DS, MPFS_DDR_CSR_APB_CFG_DS);
putreg32(LIBERO_SETTING_CFG_QOFF, MPFS_DDR_CSR_APB_CFG_QOFF);
putreg32(LIBERO_SETTING_CFG_RTT, MPFS_DDR_CSR_APB_CFG_RTT);
putreg32(LIBERO_SETTING_CFG_DLL_DISABLE, MPFS_DDR_CSR_APB_CFG_DLL_DISABLE);
putreg32(LIBERO_SETTING_CFG_REF_PER, MPFS_DDR_CSR_APB_CFG_REF_PER);
putreg32(LIBERO_SETTING_CFG_STARTUP_DELAY,
MPFS_DDR_CSR_APB_CFG_STARTUP_DELAY);
putreg32(LIBERO_SETTING_CFG_MEM_COLBITS,
MPFS_DDR_CSR_APB_CFG_MEM_COLBITS);
putreg32(LIBERO_SETTING_CFG_MEM_ROWBITS,
MPFS_DDR_CSR_APB_CFG_MEM_ROWBITS);
putreg32(LIBERO_SETTING_CFG_MEM_BANKBITS,
MPFS_DDR_CSR_APB_CFG_MEM_BANKBITS);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS0,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS0);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS1,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS1);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS2,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS2);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS3,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS3);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS4,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS4);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS5,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS5);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS6,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS6);
putreg32(LIBERO_SETTING_CFG_ODT_RD_MAP_CS7,
MPFS_DDR_CSR_APB_CFG_ODT_RD_MAP_CS7);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS0,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS0);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS1,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS1);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS2,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS2);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS3,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS3);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS4,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS4);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS5,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS5);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS6,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS6);
putreg32(LIBERO_SETTING_CFG_ODT_WR_MAP_CS7,
MPFS_DDR_CSR_APB_CFG_ODT_WR_MAP_CS7);
putreg32(LIBERO_SETTING_CFG_ODT_RD_TURN_ON,
MPFS_DDR_CSR_APB_CFG_ODT_RD_TURN_ON);
putreg32(LIBERO_SETTING_CFG_ODT_WR_TURN_ON,
MPFS_DDR_CSR_APB_CFG_ODT_WR_TURN_ON);
putreg32(LIBERO_SETTING_CFG_ODT_RD_TURN_OFF,
MPFS_DDR_CSR_APB_CFG_ODT_RD_TURN_OFF);
putreg32(LIBERO_SETTING_CFG_ODT_WR_TURN_OFF,
MPFS_DDR_CSR_APB_CFG_ODT_WR_TURN_OFF);
putreg32(LIBERO_SETTING_CFG_EMR3, MPFS_DDR_CSR_APB_CFG_EMR3);
putreg32(LIBERO_SETTING_CFG_TWO_T, MPFS_DDR_CSR_APB_CFG_TWO_T);
putreg32(LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE,
MPFS_DDR_CSR_APB_CFG_TWO_T_SEL_CYCLE);
putreg32(LIBERO_SETTING_CFG_REGDIMM, MPFS_DDR_CSR_APB_CFG_REGDIMM);
putreg32(LIBERO_SETTING_CFG_MOD, MPFS_DDR_CSR_APB_CFG_MOD);
putreg32(LIBERO_SETTING_CFG_XS, MPFS_DDR_CSR_APB_CFG_XS);
putreg32(LIBERO_SETTING_CFG_XSDLL, MPFS_DDR_CSR_APB_CFG_XSDLL);
putreg32(LIBERO_SETTING_CFG_XPR, MPFS_DDR_CSR_APB_CFG_XPR);
putreg32(LIBERO_SETTING_CFG_AL_MODE, MPFS_DDR_CSR_APB_CFG_AL_MODE);
putreg32(LIBERO_SETTING_CFG_CWL, MPFS_DDR_CSR_APB_CFG_CWL);
putreg32(LIBERO_SETTING_CFG_BL_MODE, MPFS_DDR_CSR_APB_CFG_BL_MODE);
putreg32(LIBERO_SETTING_CFG_TDQS, MPFS_DDR_CSR_APB_CFG_TDQS);
putreg32(LIBERO_SETTING_CFG_RTT_WR, MPFS_DDR_CSR_APB_CFG_RTT_WR);
putreg32(LIBERO_SETTING_CFG_LP_ASR, MPFS_DDR_CSR_APB_CFG_LP_ASR);
putreg32(LIBERO_SETTING_CFG_AUTO_SR, MPFS_DDR_CSR_APB_CFG_AUTO_SR);
putreg32(LIBERO_SETTING_CFG_SRT, MPFS_DDR_CSR_APB_CFG_SRT);
putreg32(LIBERO_SETTING_CFG_ADDR_MIRROR, MPFS_DDR_CSR_APB_CFG_ADDR_MIRROR);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_TYPE, MPFS_DDR_CSR_APB_CFG_ZQ_CAL_TYPE);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_PER, MPFS_DDR_CSR_APB_CFG_ZQ_CAL_PER);
putreg32(LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN,
MPFS_DDR_CSR_APB_CFG_AUTO_ZQ_CAL_EN);
putreg32(LIBERO_SETTING_CFG_MEMORY_TYPE, MPFS_DDR_CSR_APB_CFG_MEMORY_TYPE);
putreg32(LIBERO_SETTING_CFG_ONLY_SRANK_CMDS,
MPFS_DDR_CSR_APB_CFG_ONLY_SRANK_CMDS);
putreg32(LIBERO_SETTING_CFG_NUM_RANKS, MPFS_DDR_CSR_APB_CFG_NUM_RANKS);
putreg32(LIBERO_SETTING_CFG_QUAD_RANK, MPFS_DDR_CSR_APB_CFG_QUAD_RANK);
putreg32(LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START,
MPFS_DDR_CSR_APB_CFG_EARLY_RANK_TO_WR_START);
putreg32(LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START,
MPFS_DDR_CSR_APB_CFG_EARLY_RANK_TO_RD_START);
putreg32(LIBERO_SETTING_CFG_PASR_BANK, MPFS_DDR_CSR_APB_CFG_PASR_BANK);
putreg32(LIBERO_SETTING_CFG_PASR_SEG, MPFS_DDR_CSR_APB_CFG_PASR_SEG);
putreg32(LIBERO_SETTING_INIT_MRR_MODE, MPFS_DDR_CSR_APB_INIT_MRR_MODE);
putreg32(LIBERO_SETTING_INIT_MR_W_REQ, MPFS_DDR_CSR_APB_INIT_MR_W_REQ);
putreg32(LIBERO_SETTING_INIT_MR_ADDR, MPFS_DDR_CSR_APB_INIT_MR_ADDR);
putreg32(LIBERO_SETTING_INIT_MR_WR_DATA, MPFS_DDR_CSR_APB_INIT_MR_WR_DATA);
putreg32(LIBERO_SETTING_INIT_MR_WR_MASK, MPFS_DDR_CSR_APB_INIT_MR_WR_MASK);
putreg32(LIBERO_SETTING_INIT_NOP, MPFS_DDR_CSR_APB_INIT_NOP);
putreg32(LIBERO_SETTING_CFG_INIT_DURATION,
MPFS_DDR_CSR_APB_CFG_INIT_DURATION);
putreg32(LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQINIT_CAL_DURATION);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQ_CAL_L_DURATION);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQ_CAL_S_DURATION);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQ_CAL_R_DURATION);
putreg32(LIBERO_SETTING_CFG_MRR, MPFS_DDR_CSR_APB_CFG_MRR);
putreg32(LIBERO_SETTING_CFG_MRW, MPFS_DDR_CSR_APB_CFG_MRW);
putreg32(LIBERO_SETTING_CFG_ODT_POWERDOWN,
MPFS_DDR_CSR_APB_CFG_ODT_POWERDOWN);
putreg32(LIBERO_SETTING_CFG_WL, MPFS_DDR_CSR_APB_CFG_WL);
putreg32(LIBERO_SETTING_CFG_RL, MPFS_DDR_CSR_APB_CFG_RL);
putreg32(LIBERO_SETTING_CFG_CAL_READ_PERIOD,
MPFS_DDR_CSR_APB_CFG_CAL_READ_PERIOD);
putreg32(LIBERO_SETTING_CFG_NUM_CAL_READS,
MPFS_DDR_CSR_APB_CFG_NUM_CAL_READS);
putreg32(LIBERO_SETTING_INIT_SELF_REFRESH,
MPFS_DDR_CSR_APB_INIT_SELF_REFRESH);
putreg32(LIBERO_SETTING_INIT_POWER_DOWN,
MPFS_DDR_CSR_APB_INIT_POWER_DOWN);
putreg32(LIBERO_SETTING_INIT_FORCE_WRITE,
MPFS_DDR_CSR_APB_INIT_FORCE_WRITE);
putreg32(LIBERO_SETTING_INIT_FORCE_WRITE_CS,
MPFS_DDR_CSR_APB_INIT_FORCE_WRITE_CS);
putreg32(LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE,
MPFS_DDR_CSR_APB_CFG_CTRLR_INIT_DISABLE);
putreg32(LIBERO_SETTING_INIT_RDIMM_COMPLETE,
MPFS_DDR_CSR_APB_INIT_RDIMM_COMPLETE);
putreg32(LIBERO_SETTING_CFG_RDIMM_LAT,
MPFS_DDR_CSR_APB_CFG_RDIMM_LAT);
putreg32(LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT,
MPFS_DDR_CSR_APB_CFG_RDIMM_BSIDE_INVERT);
putreg32(LIBERO_SETTING_CFG_LRDIMM,
MPFS_DDR_CSR_APB_CFG_LRDIMM);
putreg32(LIBERO_SETTING_INIT_MEMORY_RESET_MASK,
MPFS_DDR_CSR_APB_INIT_MEMORY_RESET_MASK);
putreg32(LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE,
MPFS_DDR_CSR_APB_CFG_RD_PREAMB_TOGGLE);
putreg32(LIBERO_SETTING_CFG_RD_POSTAMBLE,
MPFS_DDR_CSR_APB_CFG_RD_POSTAMBLE);
putreg32(LIBERO_SETTING_CFG_PU_CAL, MPFS_DDR_CSR_APB_CFG_PU_CAL);
putreg32(LIBERO_SETTING_CFG_DQ_ODT, MPFS_DDR_CSR_APB_CFG_DQ_ODT);
putreg32(LIBERO_SETTING_CFG_CA_ODT, MPFS_DDR_CSR_APB_CFG_CA_ODT);
putreg32(LIBERO_SETTING_CFG_ZQLATCH_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQLATCH_DURATION);
putreg32(LIBERO_SETTING_INIT_CAL_SELECT,
MPFS_DDR_CSR_APB_INIT_CAL_SELECT);
putreg32(LIBERO_SETTING_INIT_CAL_L_R_REQ,
MPFS_DDR_CSR_APB_INIT_CAL_L_R_REQ);
putreg32(LIBERO_SETTING_INIT_CAL_L_B_SIZE,
MPFS_DDR_CSR_APB_INIT_CAL_L_B_SIZE);
putreg32(LIBERO_SETTING_INIT_RWFIFO, MPFS_DDR_CSR_APB_INIT_RWFIFO);
putreg32(LIBERO_SETTING_INIT_RD_DQCAL, MPFS_DDR_CSR_APB_INIT_RD_DQCAL);
putreg32(LIBERO_SETTING_INIT_START_DQSOSC,
MPFS_DDR_CSR_APB_INIT_START_DQSOSC);
putreg32(LIBERO_SETTING_INIT_STOP_DQSOSC,
MPFS_DDR_CSR_APB_INIT_STOP_DQSOSC);
putreg32(LIBERO_SETTING_INIT_ZQ_CAL_START,
MPFS_DDR_CSR_APB_INIT_ZQ_CAL_START);
putreg32(LIBERO_SETTING_CFG_WR_POSTAMBLE,
MPFS_DDR_CSR_APB_CFG_WR_POSTAMBLE);
putreg32(LIBERO_SETTING_INIT_CAL_L_ADDR_0,
MPFS_DDR_CSR_APB_INIT_CAL_L_ADDR_0);
putreg32(LIBERO_SETTING_INIT_CAL_L_ADDR_1,
MPFS_DDR_CSR_APB_INIT_CAL_L_ADDR_1);
putreg32(LIBERO_SETTING_CFG_CTRLUPD_TRIG,
MPFS_DDR_CSR_APB_CFG_CTRLUPD_TRIG);
putreg32(LIBERO_SETTING_CFG_CTRLUPD_START_DELAY,
MPFS_DDR_CSR_APB_CFG_CTRLUPD_START_DELAY);
putreg32(LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX,
MPFS_DDR_CSR_APB_CFG_DFI_T_CTRLUPD_MAX);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_SEL,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_SEL);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_VALUE);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_TURN_OFF_DELAY);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WIN,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_RESTART_HOLDOFF);
putreg32(LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY,
MPFS_DDR_CSR_APB_CFG_PARITY_RDIMM_DELAY);
putreg32(LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE,
MPFS_DDR_CSR_APB_CFG_CTRLR_BUSY_ENABLE);
putreg32(LIBERO_SETTING_CFG_ASYNC_ODT,
MPFS_DDR_CSR_APB_CFG_ASYNC_ODT);
putreg32(LIBERO_SETTING_CFG_ZQ_CAL_DURATION,
MPFS_DDR_CSR_APB_CFG_ZQ_CAL_DURATION);
putreg32(LIBERO_SETTING_CFG_MRRI, MPFS_DDR_CSR_APB_CFG_MRRI);
putreg32(LIBERO_SETTING_INIT_ODT_FORCE_EN,
MPFS_DDR_CSR_APB_INIT_ODT_FORCE_EN);
putreg32(LIBERO_SETTING_INIT_ODT_FORCE_RANK,
MPFS_DDR_CSR_APB_INIT_ODT_FORCE_RANK);
putreg32(LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY,
MPFS_DDR_CSR_APB_CFG_PHYUPD_ACK_DELAY);
putreg32(LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1,
MPFS_DDR_CSR_APB_CFG_MIRROR_X16_BG0_BG1);
putreg32(LIBERO_SETTING_INIT_PDA_MR_W_REQ,
MPFS_DDR_CSR_APB_INIT_PDA_MR_W_REQ);
putreg32(LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT,
MPFS_DDR_CSR_APB_INIT_PDA_NIBBLE_SELECT);
putreg32(LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_RFH,
MPFS_DDR_CSR_APB_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH);
putreg32(LIBERO_SETTING_CFG_CKSRE, MPFS_DDR_CSR_APB_CFG_CKSRE);
putreg32(LIBERO_SETTING_CFG_CKSRX, MPFS_DDR_CSR_APB_CFG_CKSRX);
putreg32(LIBERO_SETTING_CFG_RCD_STAB, MPFS_DDR_CSR_APB_CFG_RCD_STAB);
putreg32(LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY,
MPFS_DDR_CSR_APB_CFG_DFI_T_CTRL_DELAY);
putreg32(LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE,
MPFS_DDR_CSR_APB_CFG_DFI_T_DRAM_CLK_ENABLE);
putreg32(LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH,
MPFS_DDR_CSR_APB_CFG_IDLE_TIME_TO_SELF_REFRESH);
putreg32(LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN,
MPFS_DDR_CSR_APB_CFG_IDLE_TIME_TO_POWER_DOWN);
putreg32(LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF,
MPFS_DDR_CSR_APB_CFG_BURST_RW_REFRESH_HOLDOFF);
putreg32(LIBERO_SETTING_CFG_BG_INTERLEAVE,
MPFS_DDR_CSR_APB_CFG_BG_INTERLEAVE);
putreg32(LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING,
MPFS_DDR_CSR_APB_CFG_REFRESH_DURING_PHY_TRAINING);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P0);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P1);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P2);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P3);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P4);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P5);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P6);
putreg32(LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7,
MPFS_DDR_CSR_APB_CFG_STARVE_TIMEOUT_P7);
putreg32(LIBERO_SETTING_CFG_REORDER_EN,
MPFS_DDR_CSR_APB_CFG_REORDER_EN);
putreg32(LIBERO_SETTING_CFG_REORDER_QUEUE_EN,
MPFS_DDR_CSR_APB_CFG_REORDER_QUEUE_EN);
putreg32(LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN,
MPFS_DDR_CSR_APB_CFG_INTRAPORT_REORDER_EN);
putreg32(LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN,
MPFS_DDR_CSR_APB_CFG_MAINTAIN_COHERENCY);
putreg32(LIBERO_SETTING_CFG_Q_AGE_LIMIT,
MPFS_DDR_CSR_APB_CFG_Q_AGE_LIMIT);
putreg32(LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY,
MPFS_DDR_CSR_APB_CFG_RO_CLOSED_PAGE_POLICY);
putreg32(LIBERO_SETTING_CFG_REORDER_RW_ONLY,
MPFS_DDR_CSR_APB_CFG_REORDER_RW_ONLY);
putreg32(LIBERO_SETTING_CFG_RO_PRIORITY_EN,
MPFS_DDR_CSR_APB_CFG_RO_PRIORITY_EN);
putreg32(LIBERO_SETTING_CFG_DM_EN, MPFS_DDR_CSR_APB_CFG_DM_EN);
putreg32(LIBERO_SETTING_CFG_RMW_EN, MPFS_DDR_CSR_APB_CFG_RMW_EN);
putreg32(LIBERO_SETTING_CFG_ECC_CORRECTION_EN,
MPFS_DDR_CSR_APB_CFG_ECC_CORRECTION_EN);
putreg32(LIBERO_SETTING_CFG_ECC_BYPASS,
MPFS_DDR_CSR_APB_CFG_ECC_BYPASS);
putreg32(LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN,
MPFS_DDR_CSR_APB_INIT_WRITE_DATA_1B_ECC_ERROR_GEN);
putreg32(LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN,
MPFS_DDR_CSR_APB_INIT_WRITE_DATA_2B_ECC_ERROR_GEN);
putreg32(LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH,
MPFS_DDR_CSR_APB_CFG_ECC_1BIT_INT_THRESH);
putreg32(LIBERO_SETTING_INIT_READ_CAPTURE_ADDR,
MPFS_DDR_CSR_APB_INIT_READ_CAPTURE_ADDR);
putreg32(LIBERO_SETTING_CFG_ERROR_GROUP_SEL,
MPFS_DDR_CSR_APB_CFG_ERROR_GROUP_SEL);
putreg32(LIBERO_SETTING_CFG_DATA_SEL,
MPFS_DDR_CSR_APB_CFG_DATA_SEL);
putreg32(LIBERO_SETTING_CFG_TRIG_MODE,
MPFS_DDR_CSR_APB_CFG_TRIG_MODE);
putreg32(LIBERO_SETTING_CFG_POST_TRIG_CYCS,
MPFS_DDR_CSR_APB_CFG_POST_TRIG_CYCS);
putreg32(LIBERO_SETTING_CFG_TRIG_MASK,
MPFS_DDR_CSR_APB_CFG_TRIG_MASK);
putreg32(LIBERO_SETTING_CFG_EN_MASK,
MPFS_DDR_CSR_APB_CFG_EN_MASK);
putreg32(LIBERO_SETTING_MTC_ACQ_ADDR, MPFS_DDR_CSR_APB_MTC_ACQ_ADDR);
putreg32(LIBERO_SETTING_CFG_TRIG_MT_ADDR_0,
MPFS_DDR_CSR_APB_CFG_TRIG_MT_ADDR_0);
putreg32(LIBERO_SETTING_CFG_TRIG_MT_ADDR_1,
MPFS_DDR_CSR_APB_CFG_TRIG_MT_ADDR_1);
putreg32(LIBERO_SETTING_CFG_TRIG_ERR_MASK_0,
MPFS_DDR_CSR_APB_MT_ERROR_MASK_0);
putreg32(LIBERO_SETTING_CFG_TRIG_ERR_MASK_1,
MPFS_DDR_CSR_APB_MT_ERROR_MASK_1);
putreg32(LIBERO_SETTING_CFG_TRIG_ERR_MASK_2,
MPFS_DDR_CSR_APB_MT_ERROR_MASK_2);
putreg32(LIBERO_SETTING_CFG_TRIG_ERR_MASK_3,
MPFS_DDR_CSR_APB_MT_ERROR_MASK_3);
putreg32(LIBERO_SETTING_CFG_TRIG_ERR_MASK_4,
MPFS_DDR_CSR_APB_MT_ERROR_MASK_4);
putreg32(LIBERO_SETTING_MTC_ACQ_WR_DATA_0,
MPFS_DDR_CSR_APB_MTC_ACQ_WR_DATA_0);
putreg32(LIBERO_SETTING_MTC_ACQ_WR_DATA_1,
MPFS_DDR_CSR_APB_MTC_ACQ_WR_DATA_1);
putreg32(LIBERO_SETTING_MTC_ACQ_WR_DATA_2,
MPFS_DDR_CSR_APB_MTC_ACQ_WR_DATA_2);
putreg32(LIBERO_SETTING_CFG_PRE_TRIG_CYCS,
MPFS_DDR_CSR_APB_CFG_PRE_TRIG_CYCS);
putreg32(LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR,
MPFS_DDR_CSR_APB_CFG_DATA_SEL_FIRST_ERROR);
putreg32(LIBERO_SETTING_CFG_DQ_WIDTH, MPFS_DDR_CSR_APB_CFG_DQ_WIDTH);
putreg32(LIBERO_SETTING_CFG_ACTIVE_DQ_SEL,
MPFS_DDR_CSR_APB_CFG_ACTIVE_DQ_SEL);
putreg32(LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ,
MPFS_DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_REQ);
putreg32(LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD,
MPFS_DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_CMD);
putreg32(LIBERO_SETTING_CFG_DFI_T_RDDATA_EN,
MPFS_DDR_CSR_APB_CFG_DFI_T_RDDATA_EN);
putreg32(LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT,
MPFS_DDR_CSR_APB_CFG_DFI_T_PHY_RDLAT);
putreg32(LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT,
MPFS_DDR_CSR_APB_CFG_DFI_T_PHY_WRLAT);
putreg32(LIBERO_SETTING_CFG_DFI_PHYUPD_EN,
MPFS_DDR_CSR_APB_CFG_DFI_PHYUPD_EN);
putreg32(LIBERO_SETTING_INIT_DFI_LP_DATA_REQ,
MPFS_DDR_CSR_APB_INIT_DFI_LP_DATA_REQ);
putreg32(LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ,
MPFS_DDR_CSR_APB_INIT_DFI_LP_CTRL_REQ);
putreg32(LIBERO_SETTING_INIT_DFI_LP_WAKEUP,
MPFS_DDR_CSR_APB_INIT_DFI_LP_WAKEUP);
putreg32(LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE,
MPFS_DDR_CSR_APB_INIT_DFI_DRAM_CLK_DISABLE);
putreg32(LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE,
MPFS_DDR_CSR_APB_CFG_DFI_DATA_BYTE_DISABLE);
putreg32(LIBERO_SETTING_CFG_DFI_LVL_SEL,
MPFS_DDR_CSR_APB_CFG_DFI_LVL_SEL);
putreg32(LIBERO_SETTING_CFG_DFI_LVL_PERIODIC,
MPFS_DDR_CSR_APB_CFG_DFI_LVL_PERIODIC);
putreg32(LIBERO_SETTING_CFG_DFI_LVL_PATTERN,
MPFS_DDR_CSR_APB_CFG_DFI_LVL_PATTERN);
putreg32(LIBERO_SETTING_PHY_DFI_INIT_START,
MPFS_DDR_CSR_APB_PHY_DFI_INIT_START);
putreg32(LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0,
MPFS_DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_0);
putreg32(LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1,
MPFS_DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_1);
putreg32(LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0,
MPFS_DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_0);
putreg32(LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1,
MPFS_DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_1);
putreg32(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0,
MPFS_DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_0);
putreg32(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1,
MPFS_DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_1);
putreg32(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0,
MPFS_DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_0);
putreg32(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1,
MPFS_DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_1);
putreg32(LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0,
MPFS_DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_0);
putreg32(LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1,
MPFS_DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_1);
putreg32(LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0,
MPFS_DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_0);
putreg32(LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1,
MPFS_DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_1);
putreg32(LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1,
MPFS_DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI1);
putreg32(LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2,
MPFS_DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI2);
putreg32(LIBERO_SETTING_CFG_AXI_AUTO_PCH,
MPFS_DDR_CSR_APB_CFG_AXI_AUTO_PCH);
putreg32(LIBERO_SETTING_PHY_RESET_CONTROL,
MPFS_DDR_CSR_APB_PHY_RESET_CONTROL);
modifyreg32(MPFS_DDR_CSR_APB_PHY_RESET_CONTROL, 0x8000, 0);
putreg32(LIBERO_SETTING_PHY_PC_RANK, MPFS_DDR_CSR_APB_PHY_PC_RANK);
putreg32(LIBERO_SETTING_PHY_RANKS_TO_TRAIN,
MPFS_DDR_CSR_APB_PHY_RANKS_TO_TRAIN);
putreg32(LIBERO_SETTING_PHY_WRITE_REQUEST,
MPFS_DDR_CSR_APB_PHY_WRITE_REQUEST);
putreg32(LIBERO_SETTING_PHY_READ_REQUEST,
MPFS_DDR_CSR_APB_PHY_READ_REQUEST);
putreg32(LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY,
MPFS_DDR_CSR_APB_PHY_WRITE_LEVEL_DELAY);
putreg32(LIBERO_SETTING_PHY_GATE_TRAIN_DELAY,
MPFS_DDR_CSR_APB_PHY_GATE_TRAIN_DELAY);
putreg32(LIBERO_SETTING_PHY_EYE_TRAIN_DELAY,
MPFS_DDR_CSR_APB_PHY_EYE_TRAIN_DELAY);
putreg32(LIBERO_SETTING_PHY_EYE_PAT,
MPFS_DDR_CSR_APB_PHY_EYE_PAT);
putreg32(LIBERO_SETTING_PHY_START_RECAL,
MPFS_DDR_CSR_APB_PHY_START_RECAL);
putreg32(LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC,
MPFS_DDR_CSR_APB_PHY_CLR_DFI_LVL_PERIODIC);
putreg32(LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE,
MPFS_DDR_CSR_APB_PHY_TRAIN_STEP_ENABLE);
putreg32(LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT,
MPFS_DDR_CSR_APB_PHY_LPDDR_DQ_CAL_PAT);
putreg32(LIBERO_SETTING_PHY_INDPNDT_TRAINING,
MPFS_DDR_CSR_APB_PHY_INDPNDT_TRAINING);
putreg32(LIBERO_SETTING_PHY_ENCODED_QUAD_CS,
MPFS_DDR_CSR_APB_PHY_ENCODED_QUAD_CS);
putreg32(LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE,
MPFS_DDR_CSR_APB_PHY_HALF_CLK_DLY_ENABLE);
}