in arch/arm/src/stm32/stm32_hrtim.c [5397:5585]
static int hrtim_tim_reset_set(struct stm32_hrtim_s *priv, uint8_t timer,
uint64_t reset)
{
int ret = OK;
uint32_t regval = 0;
/* Sanity checking */
if (timer == HRTIM_TIMER_MASTER || timer == HRTIM_TIMER_COMMON)
{
ret = -EINVAL;
goto errout;
}
/* First 18 bits can be written directly */
regval |= (reset & 0x3ffff);
/* TimerX reset events differ for individual timers */
switch (timer)
{
#ifdef CONFIG_STM32_HRTIM_TIMA
case HRTIM_TIMER_TIMA:
{
regval |= ((reset & HRTIM_RST_TBCMP1) ?
HRTIM_TIMARST_TIMBCMP1 : 0);
regval |= ((reset & HRTIM_RST_TBCMP2) ?
HRTIM_TIMARST_TIMBCMP2 : 0);
regval |= ((reset & HRTIM_RST_TBCMP4) ?
HRTIM_TIMARST_TIMBCMP4 : 0);
regval |= ((reset & HRTIM_RST_TCCMP1) ?
HRTIM_TIMARST_TIMCCMP1 : 0);
regval |= ((reset & HRTIM_RST_TCCMP2) ?
HRTIM_TIMARST_TIMCCMP2 : 0);
regval |= ((reset & HRTIM_RST_TCCMP4) ?
HRTIM_TIMARST_TIMCCMP4 : 0);
regval |= ((reset & HRTIM_RST_TDCMP1) ?
HRTIM_TIMARST_TIMDCMP1 : 0);
regval |= ((reset & HRTIM_RST_TDCMP2) ?
HRTIM_TIMARST_TIMDCMP2 : 0);
regval |= ((reset & HRTIM_RST_TDCMP4) ?
HRTIM_TIMARST_TIMDCMP4 : 0);
regval |= ((reset & HRTIM_RST_TECMP1) ?
HRTIM_TIMARST_TIMECMP1 : 0);
regval |= ((reset & HRTIM_RST_TECMP2) ?
HRTIM_TIMARST_TIMECMP2 : 0);
regval |= ((reset & HRTIM_RST_TECMP4) ?
HRTIM_TIMARST_TIMECMP4 : 0);
break;
}
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
case HRTIM_TIMER_TIMB:
{
regval |= ((reset & HRTIM_RST_TACMP1) ?
HRTIM_TIMBRST_TIMACMP1 : 0);
regval |= ((reset & HRTIM_RST_TACMP2) ?
HRTIM_TIMBRST_TIMACMP2 : 0);
regval |= ((reset & HRTIM_RST_TACMP4) ?
HRTIM_TIMBRST_TIMACMP4 : 0);
regval |= ((reset & HRTIM_RST_TCCMP1) ?
HRTIM_TIMBRST_TIMCCMP1 : 0);
regval |= ((reset & HRTIM_RST_TCCMP2) ?
HRTIM_TIMBRST_TIMCCMP2 : 0);
regval |= ((reset & HRTIM_RST_TCCMP4) ?
HRTIM_TIMBRST_TIMCCMP4 : 0);
regval |= ((reset & HRTIM_RST_TDCMP1) ?
HRTIM_TIMBRST_TIMDCMP1 : 0);
regval |= ((reset & HRTIM_RST_TDCMP2) ?
HRTIM_TIMBRST_TIMDCMP2 : 0);
regval |= ((reset & HRTIM_RST_TDCMP4) ?
HRTIM_TIMBRST_TIMDCMP4 : 0);
regval |= ((reset & HRTIM_RST_TECMP1) ?
HRTIM_TIMBRST_TIMECMP1 : 0);
regval |= ((reset & HRTIM_RST_TECMP2) ?
HRTIM_TIMBRST_TIMECMP2 : 0);
regval |= ((reset & HRTIM_RST_TECMP4) ?
HRTIM_TIMBRST_TIMECMP4 : 0);
break;
}
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
case HRTIM_TIMER_TIMC:
{
regval |= ((reset & HRTIM_RST_TACMP1) ?
HRTIM_TIMCRST_TIMACMP1 : 0);
regval |= ((reset & HRTIM_RST_TACMP2) ?
HRTIM_TIMCRST_TIMACMP2 : 0);
regval |= ((reset & HRTIM_RST_TACMP4) ?
HRTIM_TIMCRST_TIMACMP4 : 0);
regval |= ((reset & HRTIM_RST_TBCMP1) ?
HRTIM_TIMCRST_TIMBCMP1 : 0);
regval |= ((reset & HRTIM_RST_TBCMP2) ?
HRTIM_TIMCRST_TIMBCMP2 : 0);
regval |= ((reset & HRTIM_RST_TBCMP4) ?
HRTIM_TIMCRST_TIMBCMP4 : 0);
regval |= ((reset & HRTIM_RST_TDCMP1) ?
HRTIM_TIMCRST_TIMDCMP1 : 0);
regval |= ((reset & HRTIM_RST_TDCMP2) ?
HRTIM_TIMCRST_TIMDCMP2 : 0);
regval |= ((reset & HRTIM_RST_TDCMP4) ?
HRTIM_TIMCRST_TIMDCMP4 : 0);
regval |= ((reset & HRTIM_RST_TECMP1) ?
HRTIM_TIMCRST_TIMECMP1 : 0);
regval |= ((reset & HRTIM_RST_TECMP2) ?
HRTIM_TIMCRST_TIMECMP2 : 0);
regval |= ((reset & HRTIM_RST_TECMP4) ?
HRTIM_TIMCRST_TIMECMP4 : 0);
break;
}
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
case HRTIM_TIMER_TIMD:
{
regval |= ((reset & HRTIM_RST_TACMP1) ?
HRTIM_TIMDRST_TIMACMP1 : 0);
regval |= ((reset & HRTIM_RST_TACMP2) ?
HRTIM_TIMDRST_TIMACMP2 : 0);
regval |= ((reset & HRTIM_RST_TACMP4) ?
HRTIM_TIMDRST_TIMACMP4 : 0);
regval |= ((reset & HRTIM_RST_TBCMP1) ?
HRTIM_TIMDRST_TIMBCMP1 : 0);
regval |= ((reset & HRTIM_RST_TBCMP2) ?
HRTIM_TIMDRST_TIMBCMP2 : 0);
regval |= ((reset & HRTIM_RST_TBCMP4) ?
HRTIM_TIMDRST_TIMBCMP4 : 0);
regval |= ((reset & HRTIM_RST_TCCMP1) ?
HRTIM_TIMDRST_TIMCCMP1 : 0);
regval |= ((reset & HRTIM_RST_TCCMP2) ?
HRTIM_TIMDRST_TIMCCMP2 : 0);
regval |= ((reset & HRTIM_RST_TCCMP4) ?
HRTIM_TIMDRST_TIMCCMP4 : 0);
regval |= ((reset & HRTIM_RST_TECMP1) ?
HRTIM_TIMDRST_TIMECMP1 : 0);
regval |= ((reset & HRTIM_RST_TECMP2) ?
HRTIM_TIMDRST_TIMECMP2 : 0);
regval |= ((reset & HRTIM_RST_TECMP4) ?
HRTIM_TIMDRST_TIMECMP4 : 0);
break;
}
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
case HRTIM_TIMER_TIME:
{
regval |= ((reset & HRTIM_RST_TACMP1) ?
HRTIM_TIMERST_TIMACMP1 : 0);
regval |= ((reset & HRTIM_RST_TACMP2) ?
HRTIM_TIMERST_TIMACMP2 : 0);
regval |= ((reset & HRTIM_RST_TACMP4) ?
HRTIM_TIMERST_TIMACMP4 : 0);
regval |= ((reset & HRTIM_RST_TBCMP1) ?
HRTIM_TIMERST_TIMBCMP1 : 0);
regval |= ((reset & HRTIM_RST_TBCMP2) ?
HRTIM_TIMERST_TIMBCMP2 : 0);
regval |= ((reset & HRTIM_RST_TBCMP4) ?
HRTIM_TIMERST_TIMBCMP4 : 0);
regval |= ((reset & HRTIM_RST_TCCMP1) ?
HRTIM_TIMERST_TIMCCMP1 : 0);
regval |= ((reset & HRTIM_RST_TCCMP2) ?
HRTIM_TIMERST_TIMCCMP2 : 0);
regval |= ((reset & HRTIM_RST_TCCMP4) ?
HRTIM_TIMERST_TIMCCMP4 : 0);
regval |= ((reset & HRTIM_RST_TDCMP1) ?
HRTIM_TIMERST_TIMDCMP1 : 0);
regval |= ((reset & HRTIM_RST_TDCMP2) ?
HRTIM_TIMERST_TIMDCMP2 : 0);
regval |= ((reset & HRTIM_RST_TDCMP4) ?
HRTIM_TIMERST_TIMDCMP4 : 0);
break;
}
#endif
default:
{
ret = -EINVAL;
goto errout;
}
}
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_RSTR_OFFSET, regval);
errout:
return ret;
}