in arch/arm/src/stm32h5/stm32_tim.c [930:1295]
static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev,
uint8_t channel, stm32_tim_channel_t mode)
{
uint16_t ccmr_orig = 0;
uint16_t ccmr_val = 0;
uint16_t ccmr_mask = 0xff;
uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
DEBUGASSERT(dev != NULL);
/* Further we use range as 0..3; if channel=0 it will also overflow here */
if (--channel > 4)
{
return -EINVAL;
}
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
*/
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \
((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE)
{
return -EINVAL;
}
/* Decode configuration */
switch (mode & STM32_TIM_CH_MODE_MASK)
{
case STM32_TIM_CH_DISABLED:
break;
case STM32_TIM_CH_OUTTOGGLE:
ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT);
ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
case STM32_TIM_CH_OUTPWM:
ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) +
GTIM_CCMR1_OC1PE;
ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
return -EINVAL;
}
/* Set polarity */
if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */
if (channel & 1)
{
ccmr_val <<= 8;
ccmr_mask <<= 8;
}
if (channel > 1)
{
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
}
ccmr_orig = stm32_getreg16(dev, ccmr_offset);
ccmr_orig &= ~ccmr_mask;
ccmr_orig |= ccmr_val;
stm32_putreg16(dev, ccmr_offset, ccmr_orig);
stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
/* set GPIO */
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#ifdef CONFIG_STM32H5_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
# if defined(GPIO_TIM1_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
# endif
# if defined(GPIO_TIM1_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
# endif
# if defined(GPIO_TIM1_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
# endif
# if defined(GPIO_TIM1_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
# endif
# if defined(GPIO_TIM1_CH5OUT)
case 4:
stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break;
# endif
# if defined(GPIO_TIM1_CH6OUT)
case 5:
stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
# if defined(GPIO_TIM2_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM2_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
break;
# endif
# if defined(GPIO_TIM2_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
break;
# endif
# if defined(GPIO_TIM2_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
break;
#endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
# if defined(GPIO_TIM3_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM3_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
break;
# endif
# if defined(GPIO_TIM3_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
break;
# endif
# if defined(GPIO_TIM3_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
break;
#endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
# if defined(GPIO_TIM4_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM4_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
break;
# endif
# if defined(GPIO_TIM4_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
break;
# endif
# if defined(GPIO_TIM4_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
# if defined(GPIO_TIM5_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM5_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
break;
# endif
# if defined(GPIO_TIM5_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
break;
# endif
# if defined(GPIO_TIM5_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
# if defined(GPIO_TIM8_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
# endif
# if defined(GPIO_TIM8_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
# endif
# if defined(GPIO_TIM8_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
# endif
# if defined(GPIO_TIM8_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
# endif
# if defined(GPIO_TIM8_CH5OUT)
case 4:
stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break;
# endif
# if defined(GPIO_TIM8_CH6OUT)
case 5:
stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM12
case STM32_TIM12_BASE:
switch (channel)
{
# if defined(GPIO_TIM12_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM12_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM13
case STM32_TIM13_BASE:
switch (channel)
{
# if defined(GPIO_TIM13_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM14
case STM32_TIM14_BASE:
switch (channel)
{
# if defined(GPIO_TIM14_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM15
case STM32_TIM15_BASE:
switch (channel)
{
# if defined(GPIO_TIM15_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode);
break;
# endif
# if defined(GPIO_TIM15_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM16
case STM32_TIM16_BASE:
switch (channel)
{
# if defined(GPIO_TIM16_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
#ifdef CONFIG_STM32H5_TIM17
case STM32_TIM17_BASE:
switch (channel)
{
# if defined(GPIO_TIM17_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode);
break;
# endif
default:
return -EINVAL;
}
break;
#endif
}
return OK;
}