in vm/jitrino/src/jet/bcproc.cpp [107:188]
void Compiler::handle_ik_a(const JInst& jinst) {
if (jinst.opcode == OPCODE_IINC) {
gen_iinc(jinst.op0, jinst.op1);
return;
}
switch(jinst.opcode) {
case OPCODE_LCMP:
gen_x_cmp(jinst.opcode, i64);
return;
case OPCODE_FCMPL:
case OPCODE_FCMPG:
gen_x_cmp(jinst.opcode, flt32);
return;
case OPCODE_DCMPL:
case OPCODE_DCMPG:
gen_x_cmp(jinst.opcode, dbl64);
return;
default: break;
}
jtype opnd = jvoid;
JavaByteCodes inst = jinst.opcode;
switch(jinst.opcode) {
case OPCODE_IADD: opnd = i32; inst = OPCODE_IADD; break;
case OPCODE_LADD: opnd = i64; inst = OPCODE_IADD; break;
case OPCODE_FADD: opnd = flt32; inst = OPCODE_IADD; break;
case OPCODE_DADD: opnd = dbl64; inst = OPCODE_IADD; break;
case OPCODE_ISUB: opnd = i32; inst = OPCODE_ISUB; break;
case OPCODE_LSUB: opnd = i64; inst = OPCODE_ISUB; break;
case OPCODE_FSUB: opnd = flt32; inst = OPCODE_ISUB; break;
case OPCODE_DSUB: opnd = dbl64; inst = OPCODE_ISUB; break;
case OPCODE_IMUL: opnd = i32; inst = OPCODE_IMUL; break;
case OPCODE_LMUL: opnd = i64; inst = OPCODE_IMUL; break;
case OPCODE_FMUL: opnd = flt32; inst = OPCODE_IMUL; break;
case OPCODE_DMUL: opnd = dbl64; inst = OPCODE_IMUL; break;
case OPCODE_IDIV: opnd = i32; inst = OPCODE_IDIV; break;
case OPCODE_LDIV: opnd = i64; inst = OPCODE_IDIV; break;
case OPCODE_FDIV: opnd = flt32; inst = OPCODE_IDIV; break;
case OPCODE_DDIV: opnd = dbl64; inst = OPCODE_IDIV; break;
case OPCODE_IREM: opnd = i32; inst = OPCODE_IREM; break;
case OPCODE_LREM: opnd = i64; inst = OPCODE_IREM; break;
case OPCODE_FREM: opnd = flt32; inst = OPCODE_IREM; break;
case OPCODE_DREM: opnd = dbl64; inst = OPCODE_IREM; break;
case OPCODE_INEG: opnd = i32; inst = OPCODE_INEG; break;
case OPCODE_LNEG: opnd = i64; inst = OPCODE_INEG; break;
case OPCODE_FNEG: opnd = flt32; inst = OPCODE_INEG; break;
case OPCODE_DNEG: opnd = dbl64; inst = OPCODE_INEG; break;
case OPCODE_ISHL: opnd = i32; inst = OPCODE_ISHL; break;
case OPCODE_LSHL: opnd = i64; inst = OPCODE_ISHL; break;
case OPCODE_ISHR: opnd = i32; inst = OPCODE_ISHR; break;
case OPCODE_LSHR: opnd = i64; inst = OPCODE_ISHR; break;
case OPCODE_IUSHR: opnd = i32; inst = OPCODE_IUSHR; break;
case OPCODE_LUSHR: opnd = i64; inst = OPCODE_IUSHR; break;
case OPCODE_IAND: opnd = i32; inst = OPCODE_IAND; break;
case OPCODE_LAND: opnd = i64; inst = OPCODE_IAND; break;
case OPCODE_IOR: opnd = i32; inst = OPCODE_IOR; break;
case OPCODE_LOR: opnd = i64; inst = OPCODE_IOR; break;
case OPCODE_IXOR: opnd = i32; inst = OPCODE_IXOR; break;
case OPCODE_LXOR: opnd = i64; inst = OPCODE_IXOR; break;
default: assert(false); break;
}
if ((inst == OPCODE_IDIV || inst == OPCODE_IREM ) &&
(opnd == i32 || opnd == i64)) {
gen_check_div_by_zero(opnd, 0);
}
gen_a(inst, opnd);
}