in hw/mcu/nxp/src/ext/nxp-kinetis-sdk/drivers/fsl_dspi_edma.c [1150:1449]
status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
{
assert(NULL != handle);
assert(NULL != transfer);
/* If send/receive length is zero */
if (transfer->dataSize == 0U)
{
return kStatus_InvalidArgument;
}
/* If both send buffer and receive buffer is null */
if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData)))
{
return kStatus_InvalidArgument;
}
/* Check that we're not busy.*/
if (handle->state == (uint8_t)kDSPI_Busy)
{
return kStatus_DSPI_Busy;
}
handle->state = (uint8_t)kDSPI_Busy;
uint32_t instance = DSPI_GetInstance(base);
uint8_t whichCtar = (uint8_t)((transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT);
handle->bitsPerFrame =
(((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1U;
/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
*/
if (transfer->dataSize > DSPI_EDMA_MAX_TRANSFER_SIZE(base, (handle->bitsPerFrame)))
{
handle->state = (uint8_t)kDSPI_Idle;
return kStatus_DSPI_OutOfRange;
}
/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
if ((0U != (transfer->dataSize & 0x1U)) && (handle->bitsPerFrame > 8U))
{
handle->state = (uint8_t)kDSPI_Idle;
return kStatus_InvalidArgument;
}
EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
/* Store transfer information */
handle->txData = transfer->txData;
handle->rxData = transfer->rxData;
handle->remainingSendByteCount = transfer->dataSize;
handle->remainingReceiveByteCount = transfer->dataSize;
handle->totalByteCount = transfer->dataSize;
uint32_t wordToSend = 0;
uint8_t dummyData = DSPI_GetDummyDataInstance(base);
uint8_t dataAlreadyFed = 0;
uint8_t dataFedMax = 2;
uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base);
edma_transfer_config_t transferConfigA;
edma_transfer_config_t transferConfigC;
DSPI_StopTransfer(base);
DSPI_FlushFifo(base, true, true);
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_AllStatusFlag);
DSPI_DisableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
DSPI_StartTransfer(base);
/*if dspi has separate dma request , need not prepare data first .
else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to
slaveGetTxRegister if there is no fifo*/
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
{
/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
*/
/* If bits/frame is greater than one byte */
if (handle->bitsPerFrame > 8U)
{
while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
{
if (NULL != handle->txData)
{
wordToSend = *(handle->txData);
++handle->txData; /* Increment to next data byte */
wordToSend |= (unsigned)(*(handle->txData)) << 8U;
++handle->txData; /* Increment to next data byte */
}
else
{
wordToSend = ((uint32_t)dummyData << 8U) | dummyData;
}
handle->remainingSendByteCount -= 2U; /* decrement remainingSendByteCount by 2 */
base->PUSHR_SLAVE = wordToSend;
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
dataAlreadyFed += 2U;
/* Exit loop if send count is zero, else update local variables for next loop */
if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == (dataFedMax * 2U)))
{
break;
}
} /* End of TX FIFO fill while loop */
}
else /* Optimized for bits/frame less than or equal to one byte. */
{
while ((uint32_t)kDSPI_TxFifoFillRequestFlag ==
(DSPI_GetStatusFlags(base) & (uint32_t)kDSPI_TxFifoFillRequestFlag))
{
if (NULL != handle->txData)
{
wordToSend = *(handle->txData);
/* Increment to next data word*/
++handle->txData;
}
else
{
wordToSend = dummyData;
}
base->PUSHR_SLAVE = wordToSend;
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
DSPI_ClearStatusFlags(base, (uint32_t)kDSPI_TxFifoFillRequestFlag);
/* Decrement remainingSendByteCount*/
--handle->remainingSendByteCount;
dataAlreadyFed++;
/* Exit loop if send count is zero, else update local variables for next loop */
if ((handle->remainingSendByteCount == 0U) || (dataAlreadyFed == dataFedMax))
{
break;
}
} /* End of TX FIFO fill while loop */
}
}
/***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
if (handle->remainingReceiveByteCount > 0U)
{
EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
transferConfigA.srcAddr = (uint32_t)rxAddr;
transferConfigA.srcOffset = 0;
if (NULL != handle->rxData)
{
transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
transferConfigA.destOffset = 1;
}
else
{
transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
transferConfigA.destOffset = 0;
}
transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
if (handle->bitsPerFrame <= 8U)
{
transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
transferConfigA.minorLoopBytes = 1;
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
}
else
{
transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
transferConfigA.minorLoopBytes = 2;
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2U;
}
/* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
handle->nbytes = (uint8_t)(transferConfigA.minorLoopBytes);
EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
(const edma_transfer_config_t *)(uint32_t)&transferConfigA, NULL);
EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
(uint32_t)kEDMA_MajorInterruptEnable);
}
if (handle->remainingSendByteCount > 0U)
{
/***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
transferConfigC.destAddr = (uint32_t)txAddr;
transferConfigC.destOffset = 0;
if (NULL != handle->txData)
{
transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
transferConfigC.srcOffset = 1;
}
else
{
transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
transferConfigC.srcOffset = 0;
if (handle->bitsPerFrame <= 8U)
{
handle->txBuffIfNull = dummyData;
}
else
{
handle->txBuffIfNull = ((uint32_t)dummyData << 8U) | dummyData;
}
}
transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
if (handle->bitsPerFrame <= 8U)
{
transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
transferConfigC.minorLoopBytes = 1;
transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
}
else
{
transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
transferConfigC.minorLoopBytes = 2;
transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2U;
}
EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
(const edma_transfer_config_t *)(uint32_t)&transferConfigC, NULL);
EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
}
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
/*Set channel priority*/
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel;
uint8_t t = 0;
if (channelPriorityLow > channelPriorityHigh)
{
t = channelPriorityLow;
channelPriorityLow = channelPriorityHigh;
channelPriorityHigh = t;
}
edma_channel_Preemption_config_t preemption_config_t;
preemption_config_t.enableChannelPreemption = true;
preemption_config_t.enablePreemptAbility = true;
preemption_config_t.channelPriority = channelPriorityLow;
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
{
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
preemption_config_t.channelPriority = channelPriorityHigh;
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
}
else
{
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
preemption_config_t.channelPriority = channelPriorityHigh;
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
(const edma_channel_Preemption_config_t *)(uint32_t)&preemption_config_t);
}
/*Set the channel link.
For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C.
For DSPI instances with separate RX and TX DMA requests:
Rx DMA request -> channel_A
Tx DMA request -> channel_C */
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
{
if (handle->remainingSendByteCount > 0U)
{
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel);
}
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable);
}
else
{
DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | (uint32_t)kDSPI_TxDmaEnable);
}
return kStatus_Success;
}