hw/mcu/stm/stm32u5xx/syscfg.yml

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syscfg.defs:
    MCU_FLASH_MIN_WRITE_SIZE:
        description: >
            Specifies the required alignment for internal flash writes.
            Used internally by the newt tool.
        value: 16

    MCU_STM32U5:
        description: MCUs are of STM32U5xx family
        value: 1

    STM32_CLOCK_VOLTAGESCALING_CONFIG:
        description: Adjust voltage scale
        value: 0

    STM32_CLOCK_LSI:
        description: Enable low-speed internal clock source
        value: 0

    STM32_CLOCK_LSE:
        description: Enable low-speed external clock source (aka RTC xtal)
        value: 0

    STM32_CLOCK_LSE_BYPASS:
        description: 0 for 32768 xtal; 1 for input clock
        value: 0

    STM32_CLOCK_MSI:
        description: Enable multi-speed internal clock source
        value: 1

    STM32_CLOCK_MSI_CALIBRATION:
        description: MSI calibration value
        value: 'RCC_MSICALIBRATION_DEFAULT'

    STM32_CLOCK_MSI_CLOCK_RANGE:
        description: MSI clock range
        value: 'RCC_MSIRANGE_4'

    STM32_CLOCK_HSE:
        description: Enable high-speed external clock source
        value: 0

    STM32_CLOCK_HSE_BYPASS:
        description: 0 for xtal; 1 for input clock
        value: 0

    STM32_CLOCK_HSI:
        description: Enable high-speed internal clock source
        value: 1

    STM32_CLOCK_HSI_CALIBRATION:
        description: HSI calibration value
        value: 'RCC_HSICALIBRATION_DEFAULT'

    STM32_CLOCK_HSI48:
        description: Enable high-speed 48MHz internal clock source
        value: 0

    STM32_CLOCK_PLL_PLLM:
        description: PLL config M parameter
        value: 0

    STM32_CLOCK_PLL_PLLN:
        description: PLL config N parameter
        value: 0

    STM32_CLOCK_PLL_PLLP:
        description: PLL config P parameter
        value: 0

    STM32_CLOCK_PLL_PLLQ:
        description: PLL config Q parameter
        value: 0

    STM32_CLOCK_PLL_PLLR:
        description: PLL config R parameter
        value: 0

    STM32_CLOCK_PLL_BOOST_DIV:
        description: >
            Divider for PLL boost required when target SYSCLK > 55MHz.
            Must result in boot frequency being in range 4-16MHz.
            For MSI at 4MHz set it to RCC_PLLMBOOST_DIV1.
            When left to -1, boost will be off and SYSCLK must be lower then 55MHz
        value: RCC_PLLMBOOST_DIV1

    STM32_CLOCK_AHB_DIVIDER:
        description: AHB CLK1 prescaler (80MHz max)
        value: 0

    STM32_CLOCK_APB1_DIVIDER:
        description: APB low-speed prescaler (80MHz max)
        value: 0

    STM32_CLOCK_APB2_DIVIDER:
        description: APB high-speed prescaler (80MHz max)
        value: 0

    STM32_FLASH_LATENCY:
        description: Number of wait-states
        value: 0

    STM32_ENABLE_ICACHE:
        description: Enable instruction caching
        value: 1

    STM32_ENABLE_DCACHE:
        description: Enable instruction caching
        value: 1

    STM32_FLASH_PREFETCH_ENABLE:
        description: Enable pre-fetch of instructions (when latency > 0)
        value: 1

    STM32_HAL_SPI_HAS_FIFO:
        description: This MCU has a SPI with FIFO
        value: 1

    STM32_HAL_I2C_HAS_CLOCKSPEED:
        description: This MCU's I2C has no clock speed register (has TIMINGR)
        value: 0

    STM32_HAL_UART_HAS_SR:
        description: This MCU's UART uses ISR register (not SR) for status.
        value: 0

    MCU_FLASH_ERASED_VAL:
        description: Value read from erased flash.
        value: 0xff