Path	Lines of Code
hardware/chisel/build.sbt	15
hardware/chisel/project/plugins.sbt	2
hardware/chisel/scalastyle-config.xml	133
hardware/chisel/src/main/resources/verilog/VTAHostDPI.v	67
hardware/chisel/src/main/resources/verilog/VTAMemDPI.v	138
hardware/chisel/src/main/resources/verilog/VTASimDPI.v	38
hardware/chisel/src/main/scala/core/Compute.scala	207
hardware/chisel/src/main/scala/core/Configs.scala	22
hardware/chisel/src/main/scala/core/Core.scala	67
hardware/chisel/src/main/scala/core/Decode.scala	152
hardware/chisel/src/main/scala/core/EventCounters.scala	31
hardware/chisel/src/main/scala/core/Fetch.scala	33
hardware/chisel/src/main/scala/core/FetchVME64.scala	138
hardware/chisel/src/main/scala/core/FetchWideVME.scala	253
hardware/chisel/src/main/scala/core/ISA.scala	95
hardware/chisel/src/main/scala/core/Load.scala	86
hardware/chisel/src/main/scala/core/LoadUop.scala	50
hardware/chisel/src/main/scala/core/LoadUopSimple.scala	194
hardware/chisel/src/main/scala/core/Semaphore.scala	16
hardware/chisel/src/main/scala/core/Store.scala	71
hardware/chisel/src/main/scala/core/TensorAlu.scala	480
hardware/chisel/src/main/scala/core/TensorGemm.scala	588
hardware/chisel/src/main/scala/core/TensorLoad.scala	32
hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala	542
hardware/chisel/src/main/scala/core/TensorLoadSimple.scala	296
hardware/chisel/src/main/scala/core/TensorLoadWideVME.scala	540
hardware/chisel/src/main/scala/core/TensorStore.scala	28
hardware/chisel/src/main/scala/core/TensorStoreNarrowVME.scala	217
hardware/chisel/src/main/scala/core/TensorStoreWideVME.scala	203
hardware/chisel/src/main/scala/core/TensorUtil.scala	415
hardware/chisel/src/main/scala/core/package.scala	2
hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala	115
hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala	182
hardware/chisel/src/main/scala/dpi/VTASimDPI.scala	14
hardware/chisel/src/main/scala/interface/axi/AXI.scala	258
hardware/chisel/src/main/scala/shell/Configs.scala	54
hardware/chisel/src/main/scala/shell/IntelShell.scala	39
hardware/chisel/src/main/scala/shell/SimShell.scala	49
hardware/chisel/src/main/scala/shell/VCR.scala	138
hardware/chisel/src/main/scala/shell/VME.scala	262
hardware/chisel/src/main/scala/shell/VMESimple.scala	111
hardware/chisel/src/main/scala/shell/VTAShell.scala	25
hardware/chisel/src/main/scala/shell/XilinxShell.scala	77
hardware/chisel/src/main/scala/util/Config.scala	74
hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala	3
hardware/chisel/src/main/scala/util/SyncQueue.scala	374
hardware/chisel/src/main/scala/vta/Configs.scala	33
hardware/dpi/tsim_device.cc	137
hardware/intel/scripts/compile_design.tcl	160
hardware/intel/scripts/de10_nano_top.v	60
hardware/intel/scripts/ip/vta/vta_hw.tcl	156
hardware/intel/scripts/set_attrs.py	50
hardware/intel/scripts/soc_system.tcl	741
hardware/intelfocl/src/vta.cl	278
hardware/intelfocl/src/vta.h	87
hardware/xilinx/scripts/hls.tcl	122
hardware/xilinx/scripts/hsi.tcl	24
hardware/xilinx/scripts/vivado.tcl	411
hardware/xilinx/src/vta.cc	567
hardware/xilinx/src/vta.h	76