hardware/chisel/src/main/scala/core/ISA.scala (4 lines):
	- line 77: * TODO: Add VXOR to clear accumulator
	- line 78: * TODO: Use ISA object for decoding as well
	- line 79: * TODO: Eventually deprecate ISAConstants
	- line 127: // TODO: move alu id next to task id


hardware/chisel/src/main/scala/core/TensorUtil.scala (2 lines):
	- line 53: "-F- Cannot make fetch tensor narrower than data pulse. TODO: narrow fetch with tensors")
	- line 73: "-F- Cannot make fetch tensor narrower than data pulse. TODO: narrow fetch with tensors")


hardware/chisel/src/main/scala/util/SyncQueue.scala (2 lines):
	- line 96: require (entries > 3, "-F- TODO: small queue implemetation")
	- line 171: require (entries > 3, "-F- TODO: small queue implemetation")


hardware/chisel/src/main/scala/core/TensorGemm.scala (2 lines):
	- line 146: val reset = Input(Bool()) // FIXME: reset should be replaced by a load-acc instr
	- line 619: // asset fires on emulated tensorRead Direct GEMM test TODO: fix memoryManager sram read


hardware/xilinx/scripts/vivado.tcl (2 lines):
	- line 207: # TODO: derive it from vta_config.h
	- line 216: # TODO: derive it from vta_config.h


hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala (1 line):
	- line 86: // Nb of data blocks requestd, not received. TODO: smaller width parameter


config/pkg_config.py (1 line):
	- line 138: # TODO: The following parameters have not been propagated into


hardware/chisel/src/main/scala/core/TensorAlu.scala (1 line):
	- line 36: // FIXME: the following three will change once we support properly SHR and SHL