apache / tvm-vtaDuplication

Intro

For duplication, we look at places in code where there are 6 or more lines of code that are exactly the same.
Before duplication is calculated, the code is cleaned to remove empty lines, comments, and frequently duplicated constructs such as imports.
You should aim at having as little as possible (<5%) of duplicated code as high-level of duplication can lead to maintenance difficulties, poor factoring, and logical contradictions.

Learn more...

Duplication Overall

12% duplication:

12,434 cleaned lines of cleaned code (without empty lines, comments, and frequently duplicated constructs such as imports)
1,587 duplicated lines

178 duplicates

dependency graphs: 2D graph | 3D graph | 3D graph (with duplicates)...

Duplication per Extension

Duplication per Component (primary)

Duplication Between Components (50+ lines)

Download: SVG DOT (open online Graphviz editor)

From Component --> To Component	Duplicated Lines	File Pairs	Details
apps (2%) --> src (1%)	66	2 file pairs	details...
hardware (<1%) --> src (1%)	57	1 file pair	details...
include (14%) --> src (1%)	55	1 file pair	details...

Open 3D force graph...

Show more details on duplication between components...

Longest Duplicates

The list of 50 longest duplicates.

See data for all 178 duplicates...

Size	#	Folders	Files	Lines	Code
32	x 2	apps/gemm/hardware/chisel apps/tsim_example/hardware/chisel	build.sbt build.sbt	20:69 (100%) 20:69 (100%)	view
24	x 2	apps/gemm/src apps/tsim_example/src	driver.cc driver.cc	26:64 (24%) 26:64 (26%)	view
24	x 2	apps/gemm/python apps/tsim_example/python	tsim.py tsim.py	24:73 (100%) 24:73 (100%)	view
23	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoadNarrowVME.scala TensorLoadWideVME.scala	38:65 (4%) 67:94 (4%)	view
22	x 2	apps/gemm/src src/tsim	driver.cc tsim_driver.cc	32:64 (22%) 82:114 (17%)	view
22	x 2	apps/tsim_example/src src/tsim	driver.cc tsim_driver.cc	32:64 (24%) 82:114 (17%)	view
17	x 2	hardware/chisel/src/main/scala/util hardware/chisel/src/main/scala/util	SyncQueue.scala SyncQueue.scala	111:129 (5%) 186:204 (5%)	view
17	x 2	apps/gemm/src apps/tsim_example/src	driver.cc driver.cc	87:115 (17%) 80:108 (18%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl compile_design.tcl hsi.tcl	1:16 (10%) 1:16 (66%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl compile_design.tcl vivado.tcl	1:16 (10%) 1:16 (3%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl soc_system.tcl hsi.tcl	1:16 (2%) 1:16 (66%)	view
16	x 2	hardware/xilinx/scripts hardware/xilinx/scripts	tcl hls.tcl hsi.tcl	1:16 (13%) 1:16 (66%)	view
16	x 2	hardware/intel/scripts hardware/intel/scripts/ip/vta	tcl compile_design.tcl vta_hw.tcl	1:16 (10%) 1:16 (10%)	view
16	x 2	hardware/xilinx/scripts hardware/xilinx/scripts	tcl hsi.tcl vivado.tcl	1:16 (66%) 1:16 (3%)	view
16	x 2	hardware/intel/scripts/ip/vta hardware/intel/scripts	tcl vta_hw.tcl soc_system.tcl	1:16 (10%) 1:16 (2%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl compile_design.tcl hls.tcl	1:16 (10%) 1:16 (13%)	view
16	x 2	hardware/xilinx/scripts hardware/xilinx/scripts	tcl hls.tcl vivado.tcl	1:16 (13%) 1:16 (3%)	view
16	x 2	hardware/intel/scripts hardware/intel/scripts	tcl compile_design.tcl soc_system.tcl	1:16 (10%) 1:16 (2%)	view
16	x 2	hardware/intel/scripts/ip/vta hardware/xilinx/scripts	tcl vta_hw.tcl hsi.tcl	1:16 (10%) 1:16 (66%)	view
16	x 2	hardware/intel/scripts/ip/vta hardware/xilinx/scripts	tcl vta_hw.tcl hls.tcl	1:16 (10%) 1:16 (13%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl soc_system.tcl hls.tcl	1:16 (2%) 1:16 (13%)	view
16	x 2	hardware/intel/scripts/ip/vta hardware/xilinx/scripts	tcl vta_hw.tcl vivado.tcl	1:16 (10%) 1:16 (3%)	view
16	x 2	hardware/intel/scripts hardware/xilinx/scripts	tcl soc_system.tcl vivado.tcl	1:16 (2%) 1:16 (3%)	view
15	x 2	apps/gemm/hardware/chisel/src/main/scala/accel apps/tsim_example/hardwa...el/src/main/scala/accel	Accel.scala Accel.scala	47:61 (68%) 47:61 (68%)	view
14	x 2	src/dpi src/dpi	module.cc module.cc	374:387 (3%) 459:472 (3%)	view
14	x 2	include/vta/dpi src/dpi	tsim.h module.cc	78:91 (31%) 458:471 (3%)	view
14	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorUtil.scala TensorUtil.scala	106:119 (3%) 124:137 (3%)	view
14	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorUtil.scala TensorUtil.scala	87:100 (3%) 124:137 (3%)	view
14	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorUtil.scala TensorUtil.scala	87:100 (3%) 106:119 (3%)	view
13	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoadNarrowVME.scala TensorLoadWideVME.scala	550:562 (2%) 730:742 (2%)	view
13	x 2	include/vta/dpi src/dpi	tsim.h module.cc	79:91 (29%) 374:386 (3%)	view
13	x 2	hardware/chisel/src/main/scala/util hardware/chisel/src/main/scala/util	SyncQueue.scala SyncQueue.scala	59:75 (3%) 134:150 (3%)	view
13	x 2	hardware/dpi src/dpi	tsim_device.cc module.cc	64:76 (13%) 375:387 (3%)	view
13	x 2	include/vta include/vta	hw_spec.h hw_spec.h	144:168 (17%) 208:232 (17%)	view
13	x 2	src/de10nano src/de10nano	de10nano_mgr.h de10nano_mgr.h	184:196 (3%) 219:231 (3%)	view
13	x 2	hardware/dpi src/dpi	tsim_device.cc module.cc	64:76 (13%) 460:472 (3%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoadNarrowVME.scala TensorLoadSimple.scala	38:49 (2%) 37:48 (5%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	Fetch.scala FetchWideVME.scala	44:56 (52%) 43:55 (5%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoadSimple.scala TensorLoadWideVME.scala	37:48 (5%) 67:78 (2%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorStore.scala TensorStoreNarrowVME.scala	32:43 (57%) 32:43 (6%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoad.scala TensorLoadWideVME.scala	40:51 (50%) 67:78 (2%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorStore.scala TensorStoreWideVME.scala	32:43 (57%) 34:45 (7%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	Fetch.scala FetchVME64.scala	44:56 (52%) 44:56 (11%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoad.scala TensorLoadSimple.scala	40:51 (50%) 37:48 (5%)	view
12	x 2	hardware/chisel/src/main/scala/util hardware/chisel/src/main/scala/util	SyncQueue.scala SyncQueue.scala	352:363 (3%) 430:441 (3%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorLoad.scala TensorLoadNarrowVME.scala	40:51 (50%) 38:49 (2%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	TensorStoreNarrowVME.scala TensorStoreWideVME.scala	32:43 (6%) 34:45 (7%)	view
12	x 2	hardware/dpi include/vta/dpi	tsim_device.cc tsim.h	64:75 (12%) 80:91 (27%)	view
12	x 2	hardware/chisel/src/main/scala/core hardware/chisel/src/main/scala/core	FetchVME64.scala FetchWideVME.scala	44:56 (11%) 43:55 (5%)	view
11	x 2	apps/gemm/src apps/tsim_example/src	driver.cc driver.cc	133:149 (11%) 121:137 (12%)	view

Duplicated Units

The list of top 4 duplicated units.

See data for all 4 unit duplicates...

Size	#	Folders	Files	Lines	Code
13	x 2	apps/gemm/hardware/chisel apps/tsim_example/hardware/chisel	build.sbt build.sbt	24:41 24:41	view
8	x 2	apps/gemm/hardware/chisel apps/tsim_example/hardware/chisel	build.sbt build.sbt	43:55 43:55	view
8	x 2	apps/gemm/src apps/tsim_example/src	driver.cc driver.cc	133:142 121:130	view
13	x 2	apps/gemm/python apps/tsim_example/python	tsim.py tsim.py	0:0 0:0	view