apache / tvm-vta
File Change Frequency

File change frequency (churn) shows the distribution of file updates (days with at least one commit).

Overview
File Change Frequency Overall
  • There are 113 files with 14,681 lines of code.
    • 0 files changed more than 100 times (0 lines of code)
    • 0 files changed 51-100 times (0 lines of code)
    • 0 files changed 21-50 times (0 lines of code)
    • 34 files changed 6-20 times (6,110 lines of code)
    • 79 files changed 1-5 times (8,571 lines of code)
0% | 0% | 0% | 41% | 58%
Legend:
101+
51-100
21-50
6-20
1-5

explore: grouped by folders | grouped by update frequency | data
Contributors Count Frequency Overall
  • There are 113 files with 14,681 lines of code.
    • 0 files changed by more than 25 contributors (0 lines of code)
    • 0 files changed by 11-25 contributors (0 lines of code)
    • 16 files changed by 6-10 contributors (4,081 lines of code)
    • 83 files changed by 2-5 contributors (9,451 lines of code)
    • 14 files changed by 1 contributor (1,149 lines of code)
0% | 0% | 27% | 64% | 7%
Legend:
26+
11-25
6-10
2-5
1

explore: grouped by folders | grouped by contributors count | data
File Change Frequency per File Extension
scala, cc, h, py, json, sh, v, md, sbt, tcl, gitignore, txt, properties, cl, rst, xml, yaml
File Change Frequency per Extension
The number of recorded file updates
101+
51-100
21-50
6-20
1-5
scala0% | 0% | 0% | 43% | 56%
cc0% | 0% | 0% | 67% | 32%
tcl0% | 0% | 0% | 33% | 66%
py0% | 0% | 0% | 36% | 63%
h0% | 0% | 0% | 22% | 77%
sbt0% | 0% | 0% | 15% | 84%
v0% | 0% | 0% | 0% | 100%
cl0% | 0% | 0% | 0% | 100%
xml0% | 0% | 0% | 0% | 100%
File Change Frequency per Logical Decomposition
primary
primary (file change frequency)
The number of recorded file updates
101+
51-100
21-50
6-20
1-5
hardware0% | 0% | 0% | 43% | 56%
src0% | 0% | 0% | 51% | 48%
config0% | 0% | 0% | 51% | 48%
apps0% | 0% | 0% | 12% | 87%
include0% | 0% | 0% | 39% | 60%
Most Frequently Changed Files (Top 50)

See data for all files...

File# lines# unitscreatedlast modified# changes
(days)		# contributorsfirst
contributor		latest
contributor
driver.h
in include/vta
 37 - 2018-03-18 2020-03-30 16 6 moreau@cs.washington.edu tqchen@octoml.ai
sim_driver.cc
in src/sim
 471 31 2018-04-13 2020-12-11 16 8 tqchen@users.noreply.github... zhanghao@4paradigm.com
LoadUop.scala
in hardware/chisel/src/main/scala/core
 50 - 2019-06-05 2022-01-27 14 8 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
TensorLoad.scala
in hardware/chisel/src/main/scala/core
 32 - 2019-06-05 2021-09-09 12 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
pynq_driver.cc
in src/pynq
 104 13 2018-03-18 2020-05-01 12 7 moreau@cs.washington.edu zhanghaohit@gmail.com
tcl
vivado.tcl
in hardware/xilinx/scripts
 411 - 2018-03-23 2020-12-10 12 7 moreau@cs.washington.edu dstegs@gmail.com
TensorAlu.scala
in hardware/chisel/src/main/scala/core
 480 - 2019-06-05 2022-01-27 12 8 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
TensorGemm.scala
in hardware/chisel/src/main/scala/core
 588 - 2019-06-05 2021-08-20 12 7 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
TensorUtil.scala
in hardware/chisel/src/main/scala/core
 415 7 2019-06-05 2022-01-27 11 7 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
TensorStore.scala
in hardware/chisel/src/main/scala/core
 28 - 2019-06-05 2021-09-09 10 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
pynq_driver.h
in src/pynq
 36 - 2018-03-18 2020-03-30 10 4 moreau@cs.washington.edu tqchen@octoml.ai
vta_config.py
in config
 232 6 2018-07-07 2020-12-10 10 9 tianqi.tchen@gmail.com dstegs@gmail.com
hw_spec.h
in include/vta
 98 - 2018-03-18 2020-12-11 9 5 moreau@cs.washington.edu zhanghao@4paradigm.com
tsim_driver.cc
in src/tsim
 164 18 2019-06-05 2020-03-30 9 5 vegaluisjose@users.noreply.... tqchen@octoml.ai
VTAMemDPI.scala
in hardware/chisel/src/main/scala/dpi
 182 - 2019-05-08 2022-01-27 9 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
Core.scala
in hardware/chisel/src/main/scala/core
 67 - 2019-06-05 2021-06-08 8 5 vegaluisjose@users.noreply.... abhijit.davare@intel.com
VTAHostDPI.scala
in hardware/chisel/src/main/scala/dpi
 115 - 2019-05-08 2022-01-27 8 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
tsim_device.cc
in hardware/dpi
 137 6 2019-05-08 2021-09-09 8 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
VCR.scala
in hardware/chisel/src/main/scala/shell
 138 - 2019-06-05 2022-01-27 8 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
Compute.scala
in hardware/chisel/src/main/scala/core
 207 - 2019-06-05 2021-09-09 8 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
vta.cc
in hardware/xilinx/src
 567 12 2018-03-23 2020-12-04 8 8 moreau@cs.washington.edu dstegs@gmail.com
Fetch.scala
in hardware/chisel/src/main/scala/core
 33 - 2019-06-05 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
SimShell.scala
in hardware/chisel/src/main/scala/shell
 49 - 2019-06-05 2022-01-27 7 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
driver.cc
in apps/tsim_example/src
 115 9 2019-05-08 2020-03-30 7 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
tcl
hls.tcl
in hardware/xilinx/scripts
 122 - 2018-03-23 2020-09-16 7 5 moreau@cs.washington.edu vegaluisjose@users.noreply....
AXI.scala
in hardware/chisel/src/main/scala/interface/axi
 258 5 2019-06-05 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
VME.scala
in hardware/chisel/src/main/scala/shell
 262 1 2019-06-05 2022-01-27 7 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
module.cc
in src/dpi
 437 34 2019-05-08 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
build.sbt
in hardware/chisel
 15 - 2019-05-08 2022-01-27 6 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
tsim.py
in apps/tsim_example/python
 29 5 2019-06-14 2020-03-30 6 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Configs.scala
in hardware/chisel/src/main/scala/vta
 33 - 2019-06-05 2021-08-20 6 5 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
Configs.scala
in hardware/chisel/src/main/scala/shell
 54 - 2019-06-05 2020-03-30 6 4 vegaluisjose@users.noreply.... tqchen@octoml.ai
RegFile.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 68 - 2019-05-08 2020-03-30 6 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
vta.h
in hardware/xilinx/src
 76 - 2018-03-23 2020-03-30 6 5 moreau@cs.washington.edu tqchen@octoml.ai
GenericParameterizedBundle.scala
in hardware/chisel/src/main/scala/util
 3 - 2019-06-05 2022-01-27 5 4 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
VTASimDPI.scala
in hardware/chisel/src/main/scala/dpi
 14 - 2019-07-08 2021-08-23 5 4 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
Configs.scala
in hardware/chisel/src/main/scala/core
 22 - 2019-06-05 2021-06-08 5 4 vegaluisjose@users.noreply.... abhijit.davare@intel.com
Accel.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 27 - 2019-05-08 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
EventCounters.scala
in hardware/chisel/src/main/scala/core
 31 - 2019-06-14 2020-03-30 5 4 vegaluisjose@users.noreply.... tqchen@octoml.ai
v
VTAHostDPI.v
in hardware/chisel/src/main/resources/verilog
 67 - 2019-05-08 2020-03-30 5 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
Store.scala
in hardware/chisel/src/main/scala/core
 71 - 2019-06-05 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
XilinxShell.scala
in hardware/chisel/src/main/scala/shell
 77 - 2019-06-05 2021-08-20 5 4 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
Compute.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 79 - 2019-05-08 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Load.scala
in hardware/chisel/src/main/scala/core
 86 - 2019-06-05 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
ISA.scala
in hardware/chisel/src/main/scala/core
 95 2 2019-06-05 2021-04-17 5 3 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
Decode.scala
in hardware/chisel/src/main/scala/core
 152 - 2019-06-05 2021-04-17 5 3 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
plugins.sbt
in apps/tsim_example/hardware/chisel/project
 2 - 2019-05-08 2020-03-30 4 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
plugins.sbt
in hardware/chisel/project
 2 - 2019-05-08 2020-03-30 4 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Semaphore.scala
in hardware/chisel/src/main/scala/core
 16 - 2019-06-05 2020-03-30 4 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
module.h
in include/vta/dpi
 22 - 2019-05-08 2020-03-30 4 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
Files With Most Contributors (Top 50)
Based on the number of unique email addresses found in commits.

See data for all files...

File# lines# unitscreatedlast modified# changes
(days)		# contributorsfirst
contributor		latest
contributor
vta_config.py
in config
 232 6 2018-07-07 2020-12-10 10 9 tianqi.tchen@gmail.com dstegs@gmail.com
sim_driver.cc
in src/sim
 471 31 2018-04-13 2020-12-11 16 8 tqchen@users.noreply.github... zhanghao@4paradigm.com
LoadUop.scala
in hardware/chisel/src/main/scala/core
 50 - 2019-06-05 2022-01-27 14 8 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
TensorAlu.scala
in hardware/chisel/src/main/scala/core
 480 - 2019-06-05 2022-01-27 12 8 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
vta.cc
in hardware/xilinx/src
 567 12 2018-03-23 2020-12-04 8 8 moreau@cs.washington.edu dstegs@gmail.com
tcl
vivado.tcl
in hardware/xilinx/scripts
 411 - 2018-03-23 2020-12-10 12 7 moreau@cs.washington.edu dstegs@gmail.com
TensorGemm.scala
in hardware/chisel/src/main/scala/core
 588 - 2019-06-05 2021-08-20 12 7 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
pynq_driver.cc
in src/pynq
 104 13 2018-03-18 2020-05-01 12 7 moreau@cs.washington.edu zhanghaohit@gmail.com
TensorUtil.scala
in hardware/chisel/src/main/scala/core
 415 7 2019-06-05 2022-01-27 11 7 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
driver.h
in include/vta
 37 - 2018-03-18 2020-03-30 16 6 moreau@cs.washington.edu tqchen@octoml.ai
TensorLoad.scala
in hardware/chisel/src/main/scala/core
 32 - 2019-06-05 2021-09-09 12 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
TensorStore.scala
in hardware/chisel/src/main/scala/core
 28 - 2019-06-05 2021-09-09 10 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
VTAMemDPI.scala
in hardware/chisel/src/main/scala/dpi
 182 - 2019-05-08 2022-01-27 9 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
Compute.scala
in hardware/chisel/src/main/scala/core
 207 - 2019-06-05 2021-09-09 8 6 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
VME.scala
in hardware/chisel/src/main/scala/shell
 262 1 2019-06-05 2022-01-27 7 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
build.sbt
in hardware/chisel
 15 - 2019-05-08 2022-01-27 6 6 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
hw_spec.h
in include/vta
 98 - 2018-03-18 2020-12-11 9 5 moreau@cs.washington.edu zhanghao@4paradigm.com
tsim_driver.cc
in src/tsim
 164 18 2019-06-05 2020-03-30 9 5 vegaluisjose@users.noreply.... tqchen@octoml.ai
tsim_device.cc
in hardware/dpi
 137 6 2019-05-08 2021-09-09 8 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
Core.scala
in hardware/chisel/src/main/scala/core
 67 - 2019-06-05 2021-06-08 8 5 vegaluisjose@users.noreply.... abhijit.davare@intel.com
VCR.scala
in hardware/chisel/src/main/scala/shell
 138 - 2019-06-05 2022-01-27 8 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
VTAHostDPI.scala
in hardware/chisel/src/main/scala/dpi
 115 - 2019-05-08 2022-01-27 8 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
tcl
hls.tcl
in hardware/xilinx/scripts
 122 - 2018-03-23 2020-09-16 7 5 moreau@cs.washington.edu vegaluisjose@users.noreply....
AXI.scala
in hardware/chisel/src/main/scala/interface/axi
 258 5 2019-06-05 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
Fetch.scala
in hardware/chisel/src/main/scala/core
 33 - 2019-06-05 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
SimShell.scala
in hardware/chisel/src/main/scala/shell
 49 - 2019-06-05 2022-01-27 7 5 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
module.cc
in src/dpi
 437 34 2019-05-08 2021-09-09 7 5 vegaluisjose@users.noreply.... anton.a.sorokin@intel.com
vta.h
in hardware/xilinx/src
 76 - 2018-03-23 2020-03-30 6 5 moreau@cs.washington.edu tqchen@octoml.ai
Configs.scala
in hardware/chisel/src/main/scala/vta
 33 - 2019-06-05 2021-08-20 6 5 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
pynq_driver.h
in src/pynq
 36 - 2018-03-18 2020-03-30 10 4 moreau@cs.washington.edu tqchen@octoml.ai
Configs.scala
in hardware/chisel/src/main/scala/shell
 54 - 2019-06-05 2020-03-30 6 4 vegaluisjose@users.noreply.... tqchen@octoml.ai
EventCounters.scala
in hardware/chisel/src/main/scala/core
 31 - 2019-06-14 2020-03-30 5 4 vegaluisjose@users.noreply.... tqchen@octoml.ai
Configs.scala
in hardware/chisel/src/main/scala/core
 22 - 2019-06-05 2021-06-08 5 4 vegaluisjose@users.noreply.... abhijit.davare@intel.com
GenericParameterizedBundle.scala
in hardware/chisel/src/main/scala/util
 3 - 2019-06-05 2022-01-27 5 4 vegaluisjose@users.noreply.... laeufer@cs.berkeley.edu
XilinxShell.scala
in hardware/chisel/src/main/scala/shell
 77 - 2019-06-05 2021-08-20 5 4 vegaluisjose@users.noreply.... electron.kiwi@gmail.com
VTASimDPI.scala
in hardware/chisel/src/main/scala/dpi
 14 - 2019-07-08 2021-08-23 5 4 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
scalastyle-config.xml
in hardware/chisel
 133 - 2020-03-07 2021-06-23 4 4 liangfu.chen@icloud.com abhijit.davare@intel.com
IntelShell.scala
in hardware/chisel/src/main/scala/shell
 39 - 2019-07-31 2020-03-30 4 4 liangfu.chen@harman.com tqchen@octoml.ai
82 4 2019-08-26 2020-03-30 4 4 liangfu.chen@harman.com tqchen@octoml.ai
cma_api.cc
in src/de10nano
 2 - 2019-09-05 2020-03-30 3 4 liangfu.chen@harman.com tqchen@octoml.ai
RegFile.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 68 - 2019-05-08 2020-03-30 6 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
tsim.py
in apps/tsim_example/python
 29 5 2019-06-14 2020-03-30 6 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Decode.scala
in hardware/chisel/src/main/scala/core
 152 - 2019-06-05 2021-04-17 5 3 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
ISA.scala
in hardware/chisel/src/main/scala/core
 95 2 2019-06-05 2021-04-17 5 3 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
Store.scala
in hardware/chisel/src/main/scala/core
 71 - 2019-06-05 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Load.scala
in hardware/chisel/src/main/scala/core
 86 - 2019-06-05 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Accel.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 27 - 2019-05-08 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Compute.scala
in apps/tsim_example/hardware/chisel/src/main/scala/accel
 79 - 2019-05-08 2020-03-30 5 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
tcl
hsi.tcl
in hardware/xilinx/scripts
 24 - 2018-03-23 2020-03-30 4 3 moreau@cs.washington.edu tqchen@octoml.ai
plugins.sbt
in hardware/chisel/project
 2 - 2019-05-08 2020-03-30 4 3 vegaluisjose@users.noreply.... tqchen@octoml.ai
Files With Least Contributors (Top 50)
Based on the number of unique email addresses found in commits.

See data for all files...

File# lines# unitscreatedlast modified# changes
(days)		# contributorsfirst
contributor		latest
contributor
cl
vta.cl
in hardware/intelfocl/src
 278 - 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
oclfpga_device.cc
in src/oclfpga
 193 8 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
resnet_export.py
in apps/deploy
 96 3 2020-06-11 2021-03-11 2 1 huaj@xilinx.com huaj@xilinx.com
vta.h
in hardware/intelfocl/src
 87 - 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
cpp_deploy.cc
in apps/deploy
 87 2 2020-06-11 2021-03-18 2 1 huaj@xilinx.com huaj@xilinx.com
v
driver.v
in apps/verilator/add/verilog
 87 - 2021-05-03 2021-05-03 1 1 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
hw_spec_const.h
in include/vta
 73 - 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
driver.cc
in apps/verilator/add/src
 65 1 2021-05-03 2021-05-03 1 1 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
oclfpga_driver.cc
in src/oclfpga
 59 10 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
kernel.cc
in apps/verilator/add/src
 55 - 2021-05-03 2021-05-03 1 1 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
oclfpga_device.h
in src/oclfpga
 42 - 2020-12-11 2020-12-11 1 1 zhanghao@4paradigm.com zhanghao@4paradigm.com
v
add.v
in apps/verilator/add/verilog
 11 - 2021-05-03 2021-05-03 1 1 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
img_data_help.py
in apps/deploy
 10 - 2020-06-11 2020-06-11 1 1 huaj@xilinx.com huaj@xilinx.com
bitstream.py
in apps/deploy
 6 - 2020-06-11 2020-06-11 1 1 huaj@xilinx.com huaj@xilinx.com
TensorLoadNarrowVME.scala
in hardware/chisel/src/main/scala/core
 542 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
TensorLoadWideVME.scala
in hardware/chisel/src/main/scala/core
 540 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
de10nano_mgr.h
in src/de10nano
 406 28 2020-03-09 2020-03-30 2 2 61704028+pasqoc@users.norep... tqchen@octoml.ai
SyncQueue.scala
in hardware/chisel/src/main/scala/util
 374 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
TensorLoadSimple.scala
in hardware/chisel/src/main/scala/core
 296 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
FetchWideVME.scala
in hardware/chisel/src/main/scala/core
 253 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
TensorStoreNarrowVME.scala
in hardware/chisel/src/main/scala/core
 217 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
pkg_config.py
in config
 215 6 2020-03-30 2020-12-10 3 2 tqchen@octoml.ai dstegs@gmail.com
TensorStoreWideVME.scala
in hardware/chisel/src/main/scala/core
 203 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
LoadUopSimple.scala
in hardware/chisel/src/main/scala/core
 194 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
Compute.scala
in apps/gemm/hardware/chisel/src/main/scala/accel
 171 - 2019-10-10 2020-03-30 3 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
tcl
compile_design.tcl
in hardware/intel/scripts
 160 - 2019-07-31 2020-03-30 2 2 liangfu.chen@harman.com tqchen@octoml.ai
tcl
vta_hw.tcl
in hardware/intel/scripts/ip/vta
 156 - 2019-07-31 2020-03-30 2 2 liangfu.chen@harman.com tqchen@octoml.ai
FetchVME64.scala
in hardware/chisel/src/main/scala/core
 138 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
driver.cc
in apps/gemm/src
 125 9 2019-10-10 2020-03-30 3 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
v
Compute.v
in apps/tsim_example/hardware/verilog/src
 120 - 2019-06-12 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
v
RegFile.v
in apps/tsim_example/hardware/verilog/src
 116 - 2019-06-12 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
driver.cc
in apps/tsim_example/src
 115 9 2019-05-08 2020-03-30 7 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
VMESimple.scala
in hardware/chisel/src/main/scala/shell
 111 - 2021-09-09 2022-01-27 2 2 anton.a.sorokin@intel.com laeufer@cs.berkeley.edu
v
Accel.v
in apps/tsim_example/hardware/verilog/src
 91 - 2019-06-12 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
v
TestAccel.v
in apps/tsim_example/hardware/verilog/src
 90 - 2019-06-12 2020-03-30 3 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
v
VTAHostDPI.v
in hardware/chisel/src/main/resources/verilog
 67 - 2019-05-08 2020-03-30 5 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
RegFile.scala
in apps/gemm/hardware/chisel/src/main/scala/accel
 67 - 2019-10-10 2020-03-30 3 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
v
de10_nano_top.v
in hardware/intel/scripts
 60 - 2019-07-31 2020-03-30 2 2 liangfu.chen@harman.com tqchen@octoml.ai
set_attrs.py
in hardware/intel/scripts
 50 1 2019-07-31 2020-03-30 2 2 liangfu.chen@harman.com tqchen@octoml.ai
v
VTASimDPI.v
in hardware/chisel/src/main/resources/verilog
 38 - 2019-07-08 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
build.sbt
in apps/gemm/hardware/chisel
 38 2 2019-10-10 2020-03-30 2 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
build.sbt
in apps/tsim_example/hardware/chisel
 38 2 2019-05-08 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
de10nano_driver.h
in src/de10nano
 30 - 2019-09-05 2020-03-30 2 2 liangfu.chen@harman.com tqchen@octoml.ai
Accel.scala
in apps/gemm/hardware/chisel/src/main/scala/accel
 27 - 2019-10-10 2020-03-30 2 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
module.h
in include/vta/dpi
 22 - 2019-05-08 2020-03-30 4 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
package.scala
in hardware/chisel/src/main/scala/core
 2 - 2019-06-05 2020-03-30 2 2 vegaluisjose@users.noreply.... tqchen@octoml.ai
plugins.sbt
in apps/gemm/hardware/chisel/project
 1 - 2019-10-10 2020-03-30 2 2 tu.benjamin1115@gmail.com tqchen@octoml.ai
tcl
soc_system.tcl
in hardware/intel/scripts
 741 - 2019-07-31 2020-03-30 3 3 liangfu.chen@harman.com tqchen@octoml.ai
sim_tlpp.cc
in src/sim
 160 10 2019-09-07 2020-03-30 3 3 huaj@xilinx.com tqchen@octoml.ai
Decode.scala
in hardware/chisel/src/main/scala/core
 152 - 2019-06-05 2021-04-17 5 3 vegaluisjose@users.noreply.... vegaluisjose@users.noreply....
Correlations

File Size vs. Number of Changes: 113 points

hardware/chisel/build.sbt x: 15 lines of code y: 6 # changes hardware/chisel/src/main/scala/core/FetchVME64.scala x: 138 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/FetchWideVME.scala x: 253 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/LoadUop.scala x: 50 lines of code y: 14 # changes hardware/chisel/src/main/scala/core/LoadUopSimple.scala x: 194 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorAlu.scala x: 480 lines of code y: 12 # changes hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala x: 542 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorLoadSimple.scala x: 296 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorLoadWideVME.scala x: 540 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorStoreNarrowVME.scala x: 217 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorStoreWideVME.scala x: 203 lines of code y: 2 # changes hardware/chisel/src/main/scala/core/TensorUtil.scala x: 415 lines of code y: 11 # changes hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala x: 115 lines of code y: 8 # changes hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala x: 182 lines of code y: 9 # changes hardware/chisel/src/main/scala/shell/SimShell.scala x: 49 lines of code y: 7 # changes hardware/chisel/src/main/scala/shell/VCR.scala x: 138 lines of code y: 8 # changes hardware/chisel/src/main/scala/shell/VME.scala x: 262 lines of code y: 7 # changes hardware/chisel/src/main/scala/shell/VMESimple.scala x: 111 lines of code y: 2 # changes hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala x: 3 lines of code y: 5 # changes hardware/chisel/src/main/scala/util/SyncQueue.scala x: 374 lines of code y: 2 # changes hardware/chisel/src/main/resources/verilog/VTAMemDPI.v x: 138 lines of code y: 3 # changes hardware/chisel/src/main/scala/core/Compute.scala x: 207 lines of code y: 8 # changes hardware/chisel/src/main/scala/core/Fetch.scala x: 33 lines of code y: 7 # changes hardware/chisel/src/main/scala/core/TensorLoad.scala x: 32 lines of code y: 12 # changes hardware/chisel/src/main/scala/core/TensorStore.scala x: 28 lines of code y: 10 # changes hardware/chisel/src/main/scala/interface/axi/AXI.scala x: 258 lines of code y: 7 # changes hardware/dpi/tsim_device.cc x: 137 lines of code y: 8 # changes include/vta/dpi/tsim.h x: 55 lines of code y: 4 # changes src/dpi/module.cc x: 437 lines of code y: 7 # changes hardware/chisel/src/main/scala/dpi/VTASimDPI.scala x: 14 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/TensorGemm.scala x: 588 lines of code y: 12 # changes hardware/chisel/src/main/scala/shell/XilinxShell.scala x: 77 lines of code y: 5 # changes hardware/chisel/src/main/scala/vta/Configs.scala x: 33 lines of code y: 6 # changes apps/deploy/python_deploy.py x: 40 lines of code y: 3 # changes hardware/chisel/scalastyle-config.xml x: 133 lines of code y: 4 # changes hardware/chisel/src/main/scala/core/Configs.scala x: 22 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/Core.scala x: 67 lines of code y: 8 # changes apps/verilator/add/src/driver.cc x: 65 lines of code y: 1 # changes apps/verilator/add/src/kernel.cc x: 55 lines of code y: 1 # changes apps/verilator/add/verilog/add.v x: 11 lines of code y: 1 # changes apps/verilator/add/verilog/driver.v x: 87 lines of code y: 1 # changes hardware/chisel/src/main/scala/core/Decode.scala x: 152 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/ISA.scala x: 95 lines of code y: 5 # changes apps/deploy/cpp_deploy.cc x: 87 lines of code y: 2 # changes apps/deploy/resnet_export.py x: 96 lines of code y: 2 # changes hardware/intelfocl/src/vta.cl x: 278 lines of code y: 1 # changes include/vta/hw_spec.h x: 98 lines of code y: 9 # changes include/vta/hw_spec_const.h x: 73 lines of code y: 1 # changes src/oclfpga/oclfpga_device.cc x: 193 lines of code y: 1 # changes src/oclfpga/oclfpga_device.h x: 42 lines of code y: 1 # changes src/oclfpga/oclfpga_driver.cc x: 59 lines of code y: 1 # changes src/sim/sim_driver.cc x: 471 lines of code y: 16 # changes config/pkg_config.py x: 215 lines of code y: 3 # changes config/vta_config.py x: 232 lines of code y: 10 # changes hardware/xilinx/scripts/vivado.tcl x: 411 lines of code y: 12 # changes hardware/xilinx/src/vta.cc x: 567 lines of code y: 8 # changes hardware/xilinx/scripts/hls.tcl x: 122 lines of code y: 7 # changes apps/deploy/bitstream.py x: 6 lines of code y: 1 # changes apps/deploy/img_data_help.py x: 10 lines of code y: 1 # changes src/pynq/pynq_driver.cc x: 104 lines of code y: 12 # changes apps/gemm/hardware/chisel/build.sbt x: 38 lines of code y: 2 # changes apps/gemm/hardware/chisel/project/plugins.sbt x: 1 lines of code y: 2 # changes apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala x: 27 lines of code y: 2 # changes apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala x: 171 lines of code y: 3 # changes apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala x: 67 lines of code y: 3 # changes apps/gemm/python/__init__.py x: 1 lines of code y: 3 # changes apps/gemm/python/tsim.py x: 29 lines of code y: 4 # changes apps/gemm/src/driver.cc x: 125 lines of code y: 3 # changes apps/tsim_example/hardware/chisel/project/plugins.sbt x: 2 lines of code y: 4 # changes apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala x: 27 lines of code y: 5 # changes apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala x: 79 lines of code y: 5 # changes apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala x: 68 lines of code y: 6 # changes apps/tsim_example/hardware/verilog/src/Accel.v x: 91 lines of code y: 2 # changes apps/tsim_example/hardware/verilog/src/Compute.v x: 120 lines of code y: 2 # changes apps/tsim_example/hardware/verilog/src/RegFile.v x: 116 lines of code y: 2 # changes apps/tsim_example/hardware/verilog/src/TestAccel.v x: 90 lines of code y: 3 # changes apps/tsim_example/python/tsim.py x: 29 lines of code y: 6 # changes apps/tsim_example/src/driver.cc x: 115 lines of code y: 7 # changes hardware/chisel/src/main/resources/verilog/VTAHostDPI.v x: 67 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/EventCounters.scala x: 31 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/Load.scala x: 86 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/Semaphore.scala x: 16 lines of code y: 4 # changes hardware/chisel/src/main/scala/core/Store.scala x: 71 lines of code y: 5 # changes hardware/chisel/src/main/scala/core/package.scala x: 2 lines of code y: 2 # changes hardware/chisel/src/main/scala/shell/Configs.scala x: 54 lines of code y: 6 # changes hardware/chisel/src/main/scala/shell/IntelShell.scala x: 39 lines of code y: 4 # changes hardware/chisel/src/main/scala/shell/VTAShell.scala x: 25 lines of code y: 4 # changes hardware/chisel/src/main/scala/util/Config.scala x: 74 lines of code y: 4 # changes hardware/intel/scripts/compile_design.tcl x: 160 lines of code y: 2 # changes hardware/intel/scripts/de10_nano_top.v x: 60 lines of code y: 2 # changes hardware/intel/scripts/ip/vta/vta_hw.tcl x: 156 lines of code y: 2 # changes hardware/intel/scripts/set_attrs.py x: 50 lines of code y: 2 # changes hardware/intel/scripts/soc_system.tcl x: 741 lines of code y: 3 # changes hardware/xilinx/scripts/hsi.tcl x: 24 lines of code y: 4 # changes hardware/xilinx/src/vta.h x: 76 lines of code y: 6 # changes include/vta/dpi/module.h x: 22 lines of code y: 4 # changes include/vta/driver.h x: 37 lines of code y: 16 # changes include/vta/sim_tlpp.h x: 60 lines of code y: 3 # changes src/de10nano/cma_api.cc x: 2 lines of code y: 3 # changes src/de10nano/cma_api.h x: 16 lines of code y: 3 # changes src/de10nano/de10nano_driver.cc x: 118 lines of code y: 3 # changes src/de10nano/de10nano_driver.h x: 30 lines of code y: 2 # changes src/de10nano/de10nano_mgr.h x: 406 lines of code y: 2 # changes src/pynq/pynq_driver.h x: 36 lines of code y: 10 # changes src/sim/sim_tlpp.cc x: 160 lines of code y: 3 # changes src/tsim/tsim_driver.cc x: 164 lines of code y: 9 # changes src/vmem/virtual_memory.cc x: 82 lines of code y: 4 # changes src/vmem/virtual_memory.h x: 49 lines of code y: 3 # changes
16.0
# changes
  min: 1.0
  average: 4.68
  25th percentile: 2.0
  median: 4.0
  75th percentile: 6.5
  max: 16.0
0 741.0
lines of code
min: 1.0 | average: 129.92 | 25th percentile: 33.0 | median: 77.0 | 75th percentile: 160.0 | max: 741.0

Number of Contributors vs. Number of Changes: 113 points

hardware/chisel/build.sbt x: 6 # contributors y: 6 # changes hardware/chisel/src/main/scala/core/FetchVME64.scala x: 2 # contributors y: 2 # changes hardware/chisel/src/main/scala/core/LoadUop.scala x: 8 # contributors y: 14 # changes hardware/chisel/src/main/scala/core/TensorAlu.scala x: 8 # contributors y: 12 # changes hardware/chisel/src/main/scala/core/TensorUtil.scala x: 7 # contributors y: 11 # changes hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala x: 5 # contributors y: 8 # changes hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala x: 6 # contributors y: 9 # changes hardware/chisel/src/main/scala/shell/SimShell.scala x: 5 # contributors y: 7 # changes hardware/chisel/src/main/scala/shell/VME.scala x: 6 # contributors y: 7 # changes hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala x: 4 # contributors y: 5 # changes hardware/chisel/src/main/resources/verilog/VTAMemDPI.v x: 3 # contributors y: 3 # changes hardware/chisel/src/main/scala/core/Compute.scala x: 6 # contributors y: 8 # changes hardware/chisel/src/main/scala/core/TensorLoad.scala x: 6 # contributors y: 12 # changes hardware/chisel/src/main/scala/core/TensorStore.scala x: 6 # contributors y: 10 # changes include/vta/dpi/tsim.h x: 3 # contributors y: 4 # changes hardware/chisel/src/main/scala/core/TensorGemm.scala x: 7 # contributors y: 12 # changes hardware/chisel/src/main/scala/vta/Configs.scala x: 5 # contributors y: 6 # changes hardware/chisel/scalastyle-config.xml x: 4 # contributors y: 4 # changes apps/verilator/add/src/driver.cc x: 1 # contributors y: 1 # changes hardware/chisel/src/main/scala/core/Decode.scala x: 3 # contributors y: 5 # changes apps/deploy/cpp_deploy.cc x: 1 # contributors y: 2 # changes include/vta/hw_spec.h x: 5 # contributors y: 9 # changes src/sim/sim_driver.cc x: 8 # contributors y: 16 # changes config/pkg_config.py x: 2 # contributors y: 3 # changes config/vta_config.py x: 9 # contributors y: 10 # changes hardware/xilinx/src/vta.cc x: 8 # contributors y: 8 # changes apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala x: 3 # contributors y: 6 # changes apps/tsim_example/src/driver.cc x: 2 # contributors y: 7 # changes hardware/chisel/src/main/resources/verilog/VTAHostDPI.v x: 2 # contributors y: 5 # changes hardware/chisel/src/main/scala/shell/Configs.scala x: 4 # contributors y: 6 # changes include/vta/dpi/module.h x: 2 # contributors y: 4 # changes include/vta/driver.h x: 6 # contributors y: 16 # changes src/de10nano/cma_api.cc x: 4 # contributors y: 3 # changes src/pynq/pynq_driver.h x: 4 # contributors y: 10 # changes
16.0
# changes
  min: 1.0
  average: 4.68
  25th percentile: 2.0
  median: 4.0
  75th percentile: 6.5
  max: 16.0
0 9.0
# contributors
min: 1.0 | average: 3.35 | 25th percentile: 2.0 | median: 3.0 | 75th percentile: 5.0 | max: 9.0

Number of Contributors vs. File Size: 113 points

hardware/chisel/build.sbt x: 6 # contributors y: 15 lines of code hardware/chisel/src/main/scala/core/FetchVME64.scala x: 2 # contributors y: 138 lines of code hardware/chisel/src/main/scala/core/FetchWideVME.scala x: 2 # contributors y: 253 lines of code hardware/chisel/src/main/scala/core/LoadUop.scala x: 8 # contributors y: 50 lines of code hardware/chisel/src/main/scala/core/LoadUopSimple.scala x: 2 # contributors y: 194 lines of code hardware/chisel/src/main/scala/core/TensorAlu.scala x: 8 # contributors y: 480 lines of code hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala x: 2 # contributors y: 542 lines of code hardware/chisel/src/main/scala/core/TensorLoadSimple.scala x: 2 # contributors y: 296 lines of code hardware/chisel/src/main/scala/core/TensorStoreNarrowVME.scala x: 2 # contributors y: 217 lines of code hardware/chisel/src/main/scala/core/TensorStoreWideVME.scala x: 2 # contributors y: 203 lines of code hardware/chisel/src/main/scala/core/TensorUtil.scala x: 7 # contributors y: 415 lines of code hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala x: 5 # contributors y: 115 lines of code hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala x: 6 # contributors y: 182 lines of code hardware/chisel/src/main/scala/shell/SimShell.scala x: 5 # contributors y: 49 lines of code hardware/chisel/src/main/scala/shell/VCR.scala x: 5 # contributors y: 138 lines of code hardware/chisel/src/main/scala/shell/VME.scala x: 6 # contributors y: 262 lines of code hardware/chisel/src/main/scala/shell/VMESimple.scala x: 2 # contributors y: 111 lines of code hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala x: 4 # contributors y: 3 lines of code hardware/chisel/src/main/scala/util/SyncQueue.scala x: 2 # contributors y: 374 lines of code hardware/chisel/src/main/resources/verilog/VTAMemDPI.v x: 3 # contributors y: 138 lines of code hardware/chisel/src/main/scala/core/Compute.scala x: 6 # contributors y: 207 lines of code hardware/chisel/src/main/scala/core/Fetch.scala x: 5 # contributors y: 33 lines of code hardware/chisel/src/main/scala/core/TensorLoad.scala x: 6 # contributors y: 32 lines of code hardware/chisel/src/main/scala/core/TensorStore.scala x: 6 # contributors y: 28 lines of code hardware/chisel/src/main/scala/interface/axi/AXI.scala x: 5 # contributors y: 258 lines of code hardware/dpi/tsim_device.cc x: 5 # contributors y: 137 lines of code include/vta/dpi/tsim.h x: 3 # contributors y: 55 lines of code src/dpi/module.cc x: 5 # contributors y: 437 lines of code hardware/chisel/src/main/scala/dpi/VTASimDPI.scala x: 4 # contributors y: 14 lines of code hardware/chisel/src/main/scala/core/TensorGemm.scala x: 7 # contributors y: 588 lines of code hardware/chisel/src/main/scala/shell/XilinxShell.scala x: 4 # contributors y: 77 lines of code apps/deploy/python_deploy.py x: 3 # contributors y: 40 lines of code hardware/chisel/scalastyle-config.xml x: 4 # contributors y: 133 lines of code hardware/chisel/src/main/scala/core/Configs.scala x: 4 # contributors y: 22 lines of code hardware/chisel/src/main/scala/core/Core.scala x: 5 # contributors y: 67 lines of code apps/verilator/add/src/driver.cc x: 1 # contributors y: 65 lines of code apps/verilator/add/src/kernel.cc x: 1 # contributors y: 55 lines of code apps/verilator/add/verilog/add.v x: 1 # contributors y: 11 lines of code apps/verilator/add/verilog/driver.v x: 1 # contributors y: 87 lines of code hardware/chisel/src/main/scala/core/Decode.scala x: 3 # contributors y: 152 lines of code hardware/chisel/src/main/scala/core/ISA.scala x: 3 # contributors y: 95 lines of code apps/deploy/resnet_export.py x: 1 # contributors y: 96 lines of code hardware/intelfocl/src/vta.cl x: 1 # contributors y: 278 lines of code include/vta/hw_spec.h x: 5 # contributors y: 98 lines of code include/vta/hw_spec_const.h x: 1 # contributors y: 73 lines of code src/oclfpga/oclfpga_device.cc x: 1 # contributors y: 193 lines of code src/oclfpga/oclfpga_device.h x: 1 # contributors y: 42 lines of code src/oclfpga/oclfpga_driver.cc x: 1 # contributors y: 59 lines of code src/sim/sim_driver.cc x: 8 # contributors y: 471 lines of code config/pkg_config.py x: 2 # contributors y: 215 lines of code config/vta_config.py x: 9 # contributors y: 232 lines of code hardware/xilinx/scripts/vivado.tcl x: 7 # contributors y: 411 lines of code hardware/xilinx/src/vta.cc x: 8 # contributors y: 567 lines of code hardware/xilinx/scripts/hls.tcl x: 5 # contributors y: 122 lines of code apps/deploy/bitstream.py x: 1 # contributors y: 6 lines of code src/pynq/pynq_driver.cc x: 7 # contributors y: 104 lines of code apps/gemm/hardware/chisel/build.sbt x: 2 # contributors y: 38 lines of code apps/gemm/hardware/chisel/project/plugins.sbt x: 2 # contributors y: 1 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala x: 2 # contributors y: 27 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala x: 2 # contributors y: 171 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala x: 2 # contributors y: 67 lines of code apps/gemm/python/__init__.py x: 3 # contributors y: 1 lines of code apps/gemm/python/tsim.py x: 3 # contributors y: 29 lines of code apps/gemm/src/driver.cc x: 2 # contributors y: 125 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala x: 3 # contributors y: 79 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala x: 3 # contributors y: 68 lines of code apps/tsim_example/hardware/verilog/src/Accel.v x: 2 # contributors y: 91 lines of code apps/tsim_example/hardware/verilog/src/Compute.v x: 2 # contributors y: 120 lines of code apps/tsim_example/hardware/verilog/src/RegFile.v x: 2 # contributors y: 116 lines of code apps/tsim_example/hardware/verilog/src/TestAccel.v x: 2 # contributors y: 90 lines of code hardware/chisel/src/main/scala/core/EventCounters.scala x: 4 # contributors y: 31 lines of code hardware/chisel/src/main/scala/core/Load.scala x: 3 # contributors y: 86 lines of code hardware/chisel/src/main/scala/core/Semaphore.scala x: 3 # contributors y: 16 lines of code hardware/chisel/src/main/scala/core/Store.scala x: 3 # contributors y: 71 lines of code hardware/chisel/src/main/scala/shell/Configs.scala x: 4 # contributors y: 54 lines of code hardware/chisel/src/main/scala/shell/IntelShell.scala x: 4 # contributors y: 39 lines of code hardware/chisel/src/main/scala/shell/VTAShell.scala x: 3 # contributors y: 25 lines of code hardware/chisel/src/main/scala/util/Config.scala x: 3 # contributors y: 74 lines of code hardware/intel/scripts/compile_design.tcl x: 2 # contributors y: 160 lines of code hardware/intel/scripts/de10_nano_top.v x: 2 # contributors y: 60 lines of code hardware/intel/scripts/ip/vta/vta_hw.tcl x: 2 # contributors y: 156 lines of code hardware/intel/scripts/set_attrs.py x: 2 # contributors y: 50 lines of code hardware/intel/scripts/soc_system.tcl x: 3 # contributors y: 741 lines of code hardware/xilinx/src/vta.h x: 5 # contributors y: 76 lines of code include/vta/dpi/module.h x: 2 # contributors y: 22 lines of code include/vta/driver.h x: 6 # contributors y: 37 lines of code include/vta/sim_tlpp.h x: 3 # contributors y: 60 lines of code src/de10nano/cma_api.cc x: 4 # contributors y: 2 lines of code src/de10nano/de10nano_driver.cc x: 3 # contributors y: 118 lines of code src/de10nano/de10nano_driver.h x: 2 # contributors y: 30 lines of code src/de10nano/de10nano_mgr.h x: 2 # contributors y: 406 lines of code src/pynq/pynq_driver.h x: 4 # contributors y: 36 lines of code src/sim/sim_tlpp.cc x: 3 # contributors y: 160 lines of code src/tsim/tsim_driver.cc x: 5 # contributors y: 164 lines of code src/vmem/virtual_memory.cc x: 4 # contributors y: 82 lines of code src/vmem/virtual_memory.h x: 3 # contributors y: 49 lines of code
741.0
lines of code
  min: 1.0
  average: 129.92
  25th percentile: 33.0
  median: 77.0
  75th percentile: 160.0
  max: 741.0
0 9.0
# contributors
min: 1.0 | average: 3.35 | 25th percentile: 2.0 | median: 3.0 | 75th percentile: 5.0 | max: 9.0