apache / tvm-vta
File Size

The distribution of size of files (measured in lines of code).

Intro
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File Size Overall
0% | 20% | 36% | 22% | 20%
Legend:
1001+
501-1000
201-500
101-200
1-100


explore: grouped by folders | grouped by size | sunburst | 3D view
File Size per Extension
1001+
501-1000
201-500
101-200
1-100
scala0% | 23% | 42% | 17% | 16%
tcl0% | 45% | 25% | 27% | 1%
cc0% | 19% | 30% | 37% | 11%
py0% | 0% | 63% | 0% | 36%
h0% | 0% | 37% | 0% | 62%
cl0% | 0% | 100% | 0% | 0%
v0% | 0% | 0% | 45% | 54%
xml0% | 0% | 0% | 100% | 0%
sbt0% | 0% | 0% | 0% | 100%
File Size per Logical Decomposition
primary
1001+
501-1000
201-500
101-200
1-100
hardware0% | 30% | 37% | 19% | 13%
src0% | 0% | 55% | 31% | 13%
config0% | 0% | 100% | 0% | 0%
apps0% | 0% | 0% | 38% | 61%
include0% | 0% | 0% | 0% | 100%
Longest Files (Top 50)
File# lines# units
tcl
soc_system.tcl
in hardware/intel/scripts
 741 -
TensorGemm.scala
in hardware/chisel/src/main/scala/core
 588 -
vta.cc
in hardware/xilinx/src
 567 12
TensorLoadNarrowVME.scala
in hardware/chisel/src/main/scala/core
 542 -
TensorLoadWideVME.scala
in hardware/chisel/src/main/scala/core
 540 -
TensorAlu.scala
in hardware/chisel/src/main/scala/core
 480 -
sim_driver.cc
in src/sim
 471 31
module.cc
in src/dpi
 437 34
TensorUtil.scala
in hardware/chisel/src/main/scala/core
 415 7
tcl
vivado.tcl
in hardware/xilinx/scripts
 411 -
de10nano_mgr.h
in src/de10nano
 406 28
SyncQueue.scala
in hardware/chisel/src/main/scala/util
 374 -
TensorLoadSimple.scala
in hardware/chisel/src/main/scala/core
 296 -
cl
vta.cl
in hardware/intelfocl/src
 278 -
VME.scala
in hardware/chisel/src/main/scala/shell
 262 1
AXI.scala
in hardware/chisel/src/main/scala/interface/axi
 258 5
FetchWideVME.scala
in hardware/chisel/src/main/scala/core
 253 -
vta_config.py
in config
 232 6
TensorStoreNarrowVME.scala
in hardware/chisel/src/main/scala/core
 217 -
pkg_config.py
in config
 215 6
Compute.scala
in hardware/chisel/src/main/scala/core
 207 -
TensorStoreWideVME.scala
in hardware/chisel/src/main/scala/core
 203 -
LoadUopSimple.scala
in hardware/chisel/src/main/scala/core
 194 -
oclfpga_device.cc
in src/oclfpga
 193 8
VTAMemDPI.scala
in hardware/chisel/src/main/scala/dpi
 182 -
Compute.scala
in apps/gemm/hardware/chisel/src/main/scala/accel
 171 -
tsim_driver.cc
in src/tsim
 164 18
tcl
compile_design.tcl
in hardware/intel/scripts
 160 -
sim_tlpp.cc
in src/sim
 160 10
tcl
vta_hw.tcl
in hardware/intel/scripts/ip/vta
 156 -
Decode.scala
in hardware/chisel/src/main/scala/core
 152 -
v
VTAMemDPI.v
in hardware/chisel/src/main/resources/verilog
 138 -
FetchVME64.scala
in hardware/chisel/src/main/scala/core
 138 -
VCR.scala
in hardware/chisel/src/main/scala/shell
 138 -
tsim_device.cc
in hardware/dpi
 137 6
scalastyle-config.xml
in hardware/chisel
 133 -
driver.cc
in apps/gemm/src
 125 9
tcl
hls.tcl
in hardware/xilinx/scripts
 122 -
v
Compute.v
in apps/tsim_example/hardware/verilog/src
 120 -
de10nano_driver.cc
in src/de10nano
 118 14
v
RegFile.v
in apps/tsim_example/hardware/verilog/src
 116 -
VTAHostDPI.scala
in hardware/chisel/src/main/scala/dpi
 115 -
driver.cc
in apps/tsim_example/src
 115 9
VMESimple.scala
in hardware/chisel/src/main/scala/shell
 111 -
pynq_driver.cc
in src/pynq
 104 13
hw_spec.h
in include/vta
 98 -
resnet_export.py
in apps/deploy
 96 3
ISA.scala
in hardware/chisel/src/main/scala/core
 95 2
v
Accel.v
in apps/tsim_example/hardware/verilog/src
 91 -
v
TestAccel.v
in apps/tsim_example/hardware/verilog/src
 90 -
Files With Most Units (Top 31)
File# lines# units
module.cc
in src/dpi
 437 34
sim_driver.cc
in src/sim
 471 31
de10nano_mgr.h
in src/de10nano
 406 28
tsim_driver.cc
in src/tsim
 164 18
de10nano_driver.cc
in src/de10nano
 118 14
pynq_driver.cc
in src/pynq
 104 13
vta.cc
in hardware/xilinx/src
 567 12
Config.scala
in hardware/chisel/src/main/scala/util
 74 12
oclfpga_driver.cc
in src/oclfpga
 59 10
sim_tlpp.cc
in src/sim
 160 10
driver.cc
in apps/gemm/src
 125 9
driver.cc
in apps/tsim_example/src
 115 9
oclfpga_device.cc
in src/oclfpga
 193 8
TensorUtil.scala
in hardware/chisel/src/main/scala/core
 415 7
tsim_device.cc
in hardware/dpi
 137 6
vta_config.py
in config
 232 6
pkg_config.py
in config
 215 6
AXI.scala
in hardware/chisel/src/main/scala/interface/axi
 258 5
tsim.py
in apps/gemm/python
 29 5
tsim.py
in apps/tsim_example/python
 29 5
82 4
resnet_export.py
in apps/deploy
 96 3
ISA.scala
in hardware/chisel/src/main/scala/core
 95 2
python_deploy.py
in apps/deploy
 40 2
cpp_deploy.cc
in apps/deploy
 87 2
build.sbt
in apps/gemm/hardware/chisel
 38 2
build.sbt
in apps/tsim_example/hardware/chisel
 38 2
set_attrs.py
in hardware/intel/scripts
 50 1
VME.scala
in hardware/chisel/src/main/scala/shell
 262 1
driver.cc
in apps/verilator/add/src
 65 1
virtual_memory.h
in src/vmem
 49 1
Files With Long Lines (Top 5)

There are 5 files with lines longer than 120 characters. In total, there are 61 long lines.

File# lines# units# long lines
tcl
vivado.tcl
in hardware/xilinx/scripts
 411 - 38
tcl
compile_design.tcl
in hardware/intel/scripts
 160 - 9
vta.cc
in hardware/xilinx/src
 567 12 9
tcl
soc_system.tcl
in hardware/intel/scripts
 741 - 4
Compute.scala
in apps/gemm/hardware/chisel/src/main/scala/accel
 171 - 1
Correlations

File Size vs. Commits (all time): 113 points

hardware/chisel/build.sbt x: 6 commits (all time) y: 15 lines of code hardware/chisel/src/main/scala/core/FetchVME64.scala x: 2 commits (all time) y: 138 lines of code hardware/chisel/src/main/scala/core/FetchWideVME.scala x: 2 commits (all time) y: 253 lines of code hardware/chisel/src/main/scala/core/LoadUop.scala x: 14 commits (all time) y: 50 lines of code hardware/chisel/src/main/scala/core/LoadUopSimple.scala x: 2 commits (all time) y: 194 lines of code hardware/chisel/src/main/scala/core/TensorAlu.scala x: 12 commits (all time) y: 480 lines of code hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala x: 2 commits (all time) y: 542 lines of code hardware/chisel/src/main/scala/core/TensorLoadSimple.scala x: 2 commits (all time) y: 296 lines of code hardware/chisel/src/main/scala/core/TensorStoreNarrowVME.scala x: 2 commits (all time) y: 217 lines of code hardware/chisel/src/main/scala/core/TensorStoreWideVME.scala x: 2 commits (all time) y: 203 lines of code hardware/chisel/src/main/scala/core/TensorUtil.scala x: 11 commits (all time) y: 415 lines of code hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala x: 8 commits (all time) y: 115 lines of code hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala x: 9 commits (all time) y: 182 lines of code hardware/chisel/src/main/scala/shell/SimShell.scala x: 7 commits (all time) y: 49 lines of code hardware/chisel/src/main/scala/shell/VCR.scala x: 8 commits (all time) y: 138 lines of code hardware/chisel/src/main/scala/shell/VME.scala x: 7 commits (all time) y: 262 lines of code hardware/chisel/src/main/scala/shell/VMESimple.scala x: 2 commits (all time) y: 111 lines of code hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala x: 5 commits (all time) y: 3 lines of code hardware/chisel/src/main/scala/util/SyncQueue.scala x: 2 commits (all time) y: 374 lines of code hardware/chisel/src/main/resources/verilog/VTAMemDPI.v x: 3 commits (all time) y: 138 lines of code hardware/chisel/src/main/scala/core/Compute.scala x: 8 commits (all time) y: 207 lines of code hardware/chisel/src/main/scala/core/Fetch.scala x: 7 commits (all time) y: 33 lines of code hardware/chisel/src/main/scala/core/TensorLoad.scala x: 12 commits (all time) y: 32 lines of code hardware/chisel/src/main/scala/core/TensorStore.scala x: 10 commits (all time) y: 28 lines of code hardware/chisel/src/main/scala/interface/axi/AXI.scala x: 7 commits (all time) y: 258 lines of code hardware/dpi/tsim_device.cc x: 8 commits (all time) y: 137 lines of code include/vta/dpi/tsim.h x: 4 commits (all time) y: 55 lines of code src/dpi/module.cc x: 7 commits (all time) y: 437 lines of code hardware/chisel/src/main/scala/dpi/VTASimDPI.scala x: 5 commits (all time) y: 14 lines of code hardware/chisel/src/main/scala/core/TensorGemm.scala x: 12 commits (all time) y: 588 lines of code hardware/chisel/src/main/scala/shell/XilinxShell.scala x: 5 commits (all time) y: 77 lines of code hardware/chisel/src/main/scala/vta/Configs.scala x: 6 commits (all time) y: 33 lines of code apps/deploy/python_deploy.py x: 3 commits (all time) y: 40 lines of code hardware/chisel/scalastyle-config.xml x: 4 commits (all time) y: 133 lines of code hardware/chisel/src/main/scala/core/Configs.scala x: 5 commits (all time) y: 22 lines of code hardware/chisel/src/main/scala/core/Core.scala x: 8 commits (all time) y: 67 lines of code apps/verilator/add/src/driver.cc x: 1 commits (all time) y: 65 lines of code apps/verilator/add/src/kernel.cc x: 1 commits (all time) y: 55 lines of code apps/verilator/add/verilog/add.v x: 1 commits (all time) y: 11 lines of code apps/verilator/add/verilog/driver.v x: 1 commits (all time) y: 87 lines of code hardware/chisel/src/main/scala/core/Decode.scala x: 5 commits (all time) y: 152 lines of code hardware/chisel/src/main/scala/core/ISA.scala x: 6 commits (all time) y: 95 lines of code apps/deploy/cpp_deploy.cc x: 2 commits (all time) y: 87 lines of code apps/deploy/resnet_export.py x: 2 commits (all time) y: 96 lines of code hardware/intelfocl/src/vta.cl x: 1 commits (all time) y: 278 lines of code include/vta/hw_spec.h x: 9 commits (all time) y: 98 lines of code include/vta/hw_spec_const.h x: 1 commits (all time) y: 73 lines of code src/oclfpga/oclfpga_device.cc x: 1 commits (all time) y: 193 lines of code src/oclfpga/oclfpga_device.h x: 1 commits (all time) y: 42 lines of code src/oclfpga/oclfpga_driver.cc x: 1 commits (all time) y: 59 lines of code src/sim/sim_driver.cc x: 16 commits (all time) y: 471 lines of code config/pkg_config.py x: 3 commits (all time) y: 215 lines of code config/vta_config.py x: 10 commits (all time) y: 232 lines of code hardware/xilinx/scripts/vivado.tcl x: 12 commits (all time) y: 411 lines of code hardware/xilinx/src/vta.cc x: 9 commits (all time) y: 567 lines of code hardware/xilinx/scripts/hls.tcl x: 7 commits (all time) y: 122 lines of code apps/deploy/bitstream.py x: 1 commits (all time) y: 6 lines of code src/pynq/pynq_driver.cc x: 12 commits (all time) y: 104 lines of code apps/gemm/hardware/chisel/build.sbt x: 2 commits (all time) y: 38 lines of code apps/gemm/hardware/chisel/project/plugins.sbt x: 2 commits (all time) y: 1 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala x: 2 commits (all time) y: 27 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala x: 3 commits (all time) y: 171 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala x: 3 commits (all time) y: 67 lines of code apps/gemm/python/__init__.py x: 3 commits (all time) y: 1 lines of code apps/gemm/python/tsim.py x: 4 commits (all time) y: 29 lines of code apps/gemm/src/driver.cc x: 3 commits (all time) y: 125 lines of code apps/tsim_example/hardware/chisel/project/plugins.sbt x: 4 commits (all time) y: 2 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala x: 5 commits (all time) y: 27 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala x: 5 commits (all time) y: 79 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala x: 6 commits (all time) y: 68 lines of code apps/tsim_example/hardware/verilog/src/Accel.v x: 2 commits (all time) y: 91 lines of code apps/tsim_example/hardware/verilog/src/Compute.v x: 2 commits (all time) y: 120 lines of code apps/tsim_example/hardware/verilog/src/RegFile.v x: 2 commits (all time) y: 116 lines of code apps/tsim_example/hardware/verilog/src/TestAccel.v x: 3 commits (all time) y: 90 lines of code apps/tsim_example/python/tsim.py x: 6 commits (all time) y: 29 lines of code apps/tsim_example/src/driver.cc x: 7 commits (all time) y: 115 lines of code hardware/chisel/src/main/resources/verilog/VTAHostDPI.v x: 5 commits (all time) y: 67 lines of code hardware/chisel/src/main/scala/core/EventCounters.scala x: 5 commits (all time) y: 31 lines of code hardware/chisel/src/main/scala/core/Load.scala x: 5 commits (all time) y: 86 lines of code hardware/chisel/src/main/scala/core/Semaphore.scala x: 4 commits (all time) y: 16 lines of code hardware/chisel/src/main/scala/core/Store.scala x: 5 commits (all time) y: 71 lines of code hardware/chisel/src/main/scala/shell/Configs.scala x: 6 commits (all time) y: 54 lines of code hardware/chisel/src/main/scala/shell/IntelShell.scala x: 4 commits (all time) y: 39 lines of code hardware/chisel/src/main/scala/shell/VTAShell.scala x: 4 commits (all time) y: 25 lines of code hardware/chisel/src/main/scala/util/Config.scala x: 4 commits (all time) y: 74 lines of code hardware/intel/scripts/compile_design.tcl x: 2 commits (all time) y: 160 lines of code hardware/intel/scripts/de10_nano_top.v x: 2 commits (all time) y: 60 lines of code hardware/intel/scripts/ip/vta/vta_hw.tcl x: 2 commits (all time) y: 156 lines of code hardware/intel/scripts/set_attrs.py x: 2 commits (all time) y: 50 lines of code hardware/intel/scripts/soc_system.tcl x: 3 commits (all time) y: 741 lines of code hardware/xilinx/src/vta.h x: 6 commits (all time) y: 76 lines of code include/vta/dpi/module.h x: 4 commits (all time) y: 22 lines of code include/vta/driver.h x: 16 commits (all time) y: 37 lines of code include/vta/sim_tlpp.h x: 3 commits (all time) y: 60 lines of code src/de10nano/cma_api.cc x: 5 commits (all time) y: 2 lines of code src/de10nano/cma_api.h x: 3 commits (all time) y: 16 lines of code src/de10nano/de10nano_driver.cc x: 3 commits (all time) y: 118 lines of code src/de10nano/de10nano_driver.h x: 2 commits (all time) y: 30 lines of code src/de10nano/de10nano_mgr.h x: 2 commits (all time) y: 406 lines of code src/pynq/pynq_driver.h x: 10 commits (all time) y: 36 lines of code src/sim/sim_tlpp.cc x: 3 commits (all time) y: 160 lines of code src/tsim/tsim_driver.cc x: 9 commits (all time) y: 164 lines of code src/vmem/virtual_memory.cc x: 4 commits (all time) y: 82 lines of code src/vmem/virtual_memory.h x: 3 commits (all time) y: 49 lines of code
741.0
lines of code
  min: 1.0
  average: 129.92
  25th percentile: 33.0
  median: 77.0
  75th percentile: 160.0
  max: 741.0
0 16.0
commits (all time)
min: 1.0 | average: 4.72 | 25th percentile: 2.0 | median: 4.0 | 75th percentile: 6.5 | max: 16.0

File Size vs. Contributors (all time): 113 points

hardware/chisel/build.sbt x: 6 contributors (all time) y: 15 lines of code hardware/chisel/src/main/scala/core/FetchVME64.scala x: 2 contributors (all time) y: 138 lines of code hardware/chisel/src/main/scala/core/FetchWideVME.scala x: 2 contributors (all time) y: 253 lines of code hardware/chisel/src/main/scala/core/LoadUop.scala x: 8 contributors (all time) y: 50 lines of code hardware/chisel/src/main/scala/core/LoadUopSimple.scala x: 2 contributors (all time) y: 194 lines of code hardware/chisel/src/main/scala/core/TensorAlu.scala x: 8 contributors (all time) y: 480 lines of code hardware/chisel/src/main/scala/core/TensorLoadNarrowVME.scala x: 2 contributors (all time) y: 542 lines of code hardware/chisel/src/main/scala/core/TensorLoadSimple.scala x: 2 contributors (all time) y: 296 lines of code hardware/chisel/src/main/scala/core/TensorStoreNarrowVME.scala x: 2 contributors (all time) y: 217 lines of code hardware/chisel/src/main/scala/core/TensorStoreWideVME.scala x: 2 contributors (all time) y: 203 lines of code hardware/chisel/src/main/scala/core/TensorUtil.scala x: 7 contributors (all time) y: 415 lines of code hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala x: 5 contributors (all time) y: 115 lines of code hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala x: 6 contributors (all time) y: 182 lines of code hardware/chisel/src/main/scala/shell/SimShell.scala x: 5 contributors (all time) y: 49 lines of code hardware/chisel/src/main/scala/shell/VCR.scala x: 5 contributors (all time) y: 138 lines of code hardware/chisel/src/main/scala/shell/VME.scala x: 6 contributors (all time) y: 262 lines of code hardware/chisel/src/main/scala/shell/VMESimple.scala x: 2 contributors (all time) y: 111 lines of code hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala x: 4 contributors (all time) y: 3 lines of code hardware/chisel/src/main/scala/util/SyncQueue.scala x: 2 contributors (all time) y: 374 lines of code hardware/chisel/src/main/resources/verilog/VTAMemDPI.v x: 3 contributors (all time) y: 138 lines of code hardware/chisel/src/main/scala/core/Compute.scala x: 6 contributors (all time) y: 207 lines of code hardware/chisel/src/main/scala/core/Fetch.scala x: 5 contributors (all time) y: 33 lines of code hardware/chisel/src/main/scala/core/TensorLoad.scala x: 6 contributors (all time) y: 32 lines of code hardware/chisel/src/main/scala/core/TensorStore.scala x: 6 contributors (all time) y: 28 lines of code hardware/chisel/src/main/scala/interface/axi/AXI.scala x: 5 contributors (all time) y: 258 lines of code hardware/dpi/tsim_device.cc x: 5 contributors (all time) y: 137 lines of code include/vta/dpi/tsim.h x: 3 contributors (all time) y: 55 lines of code src/dpi/module.cc x: 5 contributors (all time) y: 437 lines of code hardware/chisel/src/main/scala/dpi/VTASimDPI.scala x: 4 contributors (all time) y: 14 lines of code hardware/chisel/src/main/scala/core/TensorGemm.scala x: 7 contributors (all time) y: 588 lines of code hardware/chisel/src/main/scala/shell/XilinxShell.scala x: 4 contributors (all time) y: 77 lines of code apps/deploy/python_deploy.py x: 3 contributors (all time) y: 40 lines of code hardware/chisel/scalastyle-config.xml x: 4 contributors (all time) y: 133 lines of code hardware/chisel/src/main/scala/core/Configs.scala x: 4 contributors (all time) y: 22 lines of code hardware/chisel/src/main/scala/core/Core.scala x: 5 contributors (all time) y: 67 lines of code apps/verilator/add/src/driver.cc x: 1 contributors (all time) y: 65 lines of code apps/verilator/add/src/kernel.cc x: 1 contributors (all time) y: 55 lines of code apps/verilator/add/verilog/add.v x: 1 contributors (all time) y: 11 lines of code apps/verilator/add/verilog/driver.v x: 1 contributors (all time) y: 87 lines of code hardware/chisel/src/main/scala/core/Decode.scala x: 3 contributors (all time) y: 152 lines of code hardware/chisel/src/main/scala/core/ISA.scala x: 3 contributors (all time) y: 95 lines of code apps/deploy/resnet_export.py x: 1 contributors (all time) y: 96 lines of code hardware/intelfocl/src/vta.cl x: 1 contributors (all time) y: 278 lines of code include/vta/hw_spec.h x: 5 contributors (all time) y: 98 lines of code include/vta/hw_spec_const.h x: 1 contributors (all time) y: 73 lines of code src/oclfpga/oclfpga_device.cc x: 1 contributors (all time) y: 193 lines of code src/oclfpga/oclfpga_device.h x: 1 contributors (all time) y: 42 lines of code src/oclfpga/oclfpga_driver.cc x: 1 contributors (all time) y: 59 lines of code src/sim/sim_driver.cc x: 8 contributors (all time) y: 471 lines of code config/pkg_config.py x: 2 contributors (all time) y: 215 lines of code config/vta_config.py x: 9 contributors (all time) y: 232 lines of code hardware/xilinx/scripts/vivado.tcl x: 7 contributors (all time) y: 411 lines of code hardware/xilinx/src/vta.cc x: 8 contributors (all time) y: 567 lines of code hardware/xilinx/scripts/hls.tcl x: 5 contributors (all time) y: 122 lines of code apps/deploy/bitstream.py x: 1 contributors (all time) y: 6 lines of code src/pynq/pynq_driver.cc x: 7 contributors (all time) y: 104 lines of code apps/gemm/hardware/chisel/build.sbt x: 2 contributors (all time) y: 38 lines of code apps/gemm/hardware/chisel/project/plugins.sbt x: 2 contributors (all time) y: 1 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Accel.scala x: 2 contributors (all time) y: 27 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/Compute.scala x: 2 contributors (all time) y: 171 lines of code apps/gemm/hardware/chisel/src/main/scala/accel/RegFile.scala x: 2 contributors (all time) y: 67 lines of code apps/gemm/python/__init__.py x: 3 contributors (all time) y: 1 lines of code apps/gemm/python/tsim.py x: 3 contributors (all time) y: 29 lines of code apps/gemm/src/driver.cc x: 2 contributors (all time) y: 125 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala x: 3 contributors (all time) y: 79 lines of code apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala x: 3 contributors (all time) y: 68 lines of code apps/tsim_example/hardware/verilog/src/Accel.v x: 2 contributors (all time) y: 91 lines of code apps/tsim_example/hardware/verilog/src/Compute.v x: 2 contributors (all time) y: 120 lines of code apps/tsim_example/hardware/verilog/src/RegFile.v x: 2 contributors (all time) y: 116 lines of code apps/tsim_example/hardware/verilog/src/TestAccel.v x: 2 contributors (all time) y: 90 lines of code hardware/chisel/src/main/scala/core/EventCounters.scala x: 4 contributors (all time) y: 31 lines of code hardware/chisel/src/main/scala/core/Load.scala x: 3 contributors (all time) y: 86 lines of code hardware/chisel/src/main/scala/core/Semaphore.scala x: 3 contributors (all time) y: 16 lines of code hardware/chisel/src/main/scala/core/Store.scala x: 3 contributors (all time) y: 71 lines of code hardware/chisel/src/main/scala/shell/Configs.scala x: 4 contributors (all time) y: 54 lines of code hardware/chisel/src/main/scala/shell/IntelShell.scala x: 4 contributors (all time) y: 39 lines of code hardware/chisel/src/main/scala/shell/VTAShell.scala x: 3 contributors (all time) y: 25 lines of code hardware/chisel/src/main/scala/util/Config.scala x: 3 contributors (all time) y: 74 lines of code hardware/intel/scripts/compile_design.tcl x: 2 contributors (all time) y: 160 lines of code hardware/intel/scripts/de10_nano_top.v x: 2 contributors (all time) y: 60 lines of code hardware/intel/scripts/ip/vta/vta_hw.tcl x: 2 contributors (all time) y: 156 lines of code hardware/intel/scripts/set_attrs.py x: 2 contributors (all time) y: 50 lines of code hardware/intel/scripts/soc_system.tcl x: 3 contributors (all time) y: 741 lines of code hardware/xilinx/src/vta.h x: 5 contributors (all time) y: 76 lines of code include/vta/dpi/module.h x: 2 contributors (all time) y: 22 lines of code include/vta/driver.h x: 6 contributors (all time) y: 37 lines of code include/vta/sim_tlpp.h x: 3 contributors (all time) y: 60 lines of code src/de10nano/cma_api.cc x: 4 contributors (all time) y: 2 lines of code src/de10nano/de10nano_driver.cc x: 3 contributors (all time) y: 118 lines of code src/de10nano/de10nano_driver.h x: 2 contributors (all time) y: 30 lines of code src/de10nano/de10nano_mgr.h x: 2 contributors (all time) y: 406 lines of code src/pynq/pynq_driver.h x: 4 contributors (all time) y: 36 lines of code src/sim/sim_tlpp.cc x: 3 contributors (all time) y: 160 lines of code src/tsim/tsim_driver.cc x: 5 contributors (all time) y: 164 lines of code src/vmem/virtual_memory.cc x: 4 contributors (all time) y: 82 lines of code src/vmem/virtual_memory.h x: 3 contributors (all time) y: 49 lines of code
741.0
lines of code
  min: 1.0
  average: 129.92
  25th percentile: 33.0
  median: 77.0
  75th percentile: 160.0
  max: 741.0
0 9.0
contributors (all time)
min: 1.0 | average: 3.35 | 25th percentile: 2.0 | median: 3.0 | 75th percentile: 5.0 | max: 9.0

File Size vs. Commits (30 days): 0 points

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File Size vs. Contributors (30 days): 0 points

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File Size vs. Commits (90 days): 0 points

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File Size vs. Contributors (90 days): 0 points

No data for "contributors (90d)" vs. "lines of code".