in hardware/chisel/src/main/scala/interface/axi/AXI.scala [158:191]
def tieoff() {
aw.valid := false.B
aw.bits.addr := 0.U
aw.bits.id := 0.U
aw.bits.user := 0.U
aw.bits.len := 0.U
aw.bits.size := 0.U
aw.bits.burst := 0.U
aw.bits.lock := 0.U
aw.bits.cache := 0.U
aw.bits.prot := 0.U
aw.bits.qos := 0.U
aw.bits.region := 0.U
w.valid := false.B
w.bits.data := 0.U
w.bits.strb := 0.U
w.bits.last := false.B
w.bits.id := 0.U
w.bits.user := 0.U
b.ready := false.B
ar.valid := false.B
ar.bits.addr := 0.U
ar.bits.id := 0.U
ar.bits.user := 0.U
ar.bits.len := 0.U
ar.bits.size := 0.U
ar.bits.burst := 0.U
ar.bits.lock := 0.U
ar.bits.cache := 0.U
ar.bits.prot := 0.U
ar.bits.qos := 0.U
ar.bits.region := 0.U
r.ready := false.B
}