def set_attrs()

in hardware/intel/scripts/set_attrs.py [0:0]


def set_attrs(fname, fname_out, dsp=False, verbose=True):
    """Set attributes to precompiled verilog code to indicate synthesis preference.

    Parameters
    ----------
    fname : str
        The name of input verilog source code file.

    fname_out : str
        The name of output verilog source code file.
    """
    out = ""
    with open(fname, 'rt') as fp:
        module = ''
        for idx, line in enumerate(fp):
            if 'module' in line:
                module = line[line.find('module')+7:line.find('(')]
                out += line
            elif " * " in line:
                if dsp:
                    line = line.replace(" * ", ' * (* multstyle="dsp" *) ')
                else:
                    line = line.replace(" * ", ' * (* multstyle="logic" *) ')
                if verbose:
                    print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
                out += line
            elif "rA;" in line:
                line = line.replace("rA;", 'rA /* synthesis noprune */;')
                if verbose:
                    print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
                out += line
            elif "rB;" in line:
                line = line.replace("rB;", 'rB /* synthesis noprune */;')
                if verbose:
                    print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
                out += line
            elif "rC;" in line:
                line = line.replace("rC;", 'rC /* synthesis noprune */;')
                if verbose:
                    print(fname_out+":"+str(idx+1)+": "+module+":"+line[1:line.find(";")+1])
                out += line
            else:
                out += line
    with open(fname_out, 'wt') as fp:
        fp.write(out)