hdk/common/ip/cl_ip/cl_ip.ip_user_files/ipstatic/verif/model/HBM_xsim.sv (22 lines): - line 846: //FIXME add timing parameter print logic - line 883: // FIXME add checker for "DM and ECC can not be enabled simultaneously". i.e., OP[1:0] = 01 is not allowed. - line 953: bit col_par = 0; // FIXME need to add cmd parity check - line 967: bit row_par = 0; // FIXME need to add cmd parity check - line 973: //hbm_bank_state_t bank_state[C_HBM_NO_OF_BANKS]; // FIXME need to add it for debugging - line 1094: t = t_q.sum()/10; // FIXME is it correct to calculate TCK as average 10 clk period? - line 1114: // FIXME do we need to initialize entire content, will it slow down simulation? - line 1439: //valid_col_cmd = 1; // FIXME do we need to consider it as valid command - line 1461: bit [C_HBM_PAGE_ADDR_WIDTH-1:0] page_addr = 0; // FIXME page_addr needs to be renamed as bank_addr? - line 1463: bit dqs_preamble_en = 1; //FIXME default to 1, need to add proper logic - line 1464: bit dqs_postamble_en = 1; //FIXME default to 1, need to add proper logic - line 1602: // FIXME need to confirm the MR2/MR4 or MR4/MR2 sequence from rtl team? no mention on spec - line 1871: //FIXME anything needs to be added? - line 1951: // //FIXME need to add - line 1954: //FIXME as per jedec spec, what is odd/even bytes in read data? - line 2038: updated_data[(i*32)+:32] = $urandom(); //FIXME all channels must generate diff set of random data. Also, every read to the same location will return different rand value within channel. shall seed it with addresss? think further about seeding.. - line 2074: rand_data[(i*32)+:32] = $urandom(); //FIXME all channels must generate diff set of random data. shall seed it with addresss? think further about seeding.. - line 2283: else begin /*Initialization Sequence*/ //FIXME need to write logic to detect initialization sequence - line 2387: //valid_row_cmd = 1; // FIXME do we need to consider it as valid command - line 2517: else `hbm_fatal(TAG, $sformatf("Sending ACTIVATE command to open Row is invalid in LEGACY Mode. %0s", get_page_info(page_addr))) //FIXME does this check required? - line 2522: //else `hbm_warning(TAG, $sformatf("Sending PRECHARGE command to closed Row is invalid. %0s", get_page_info(page_addr))) //FIXME does this check required? - line 2526: //else `hbm_warning(TAG, $sformatf("Sending PRECHARGE_ALL command while none of the Rows are opened is invalid. %0s", get_page_info(page_addr))) //FIXME does this check required? hdk/common/ip/cl_ip/cl_ip.gen/sources_1/ip/cl_hbm/verif/model/HBM_xsim.sv (22 lines): - line 846: //FIXME add timing parameter print logic - line 883: // FIXME add checker for "DM and ECC can not be enabled simultaneously". i.e., OP[1:0] = 01 is not allowed. - line 953: bit col_par = 0; // FIXME need to add cmd parity check - line 967: bit row_par = 0; // FIXME need to add cmd parity check - line 973: //hbm_bank_state_t bank_state[C_HBM_NO_OF_BANKS]; // FIXME need to add it for debugging - line 1094: t = t_q.sum()/10; // FIXME is it correct to calculate TCK as average 10 clk period? - line 1114: // FIXME do we need to initialize entire content, will it slow down simulation? - line 1439: //valid_col_cmd = 1; // FIXME do we need to consider it as valid command - line 1461: bit [C_HBM_PAGE_ADDR_WIDTH-1:0] page_addr = 0; // FIXME page_addr needs to be renamed as bank_addr? - line 1463: bit dqs_preamble_en = 1; //FIXME default to 1, need to add proper logic - line 1464: bit dqs_postamble_en = 1; //FIXME default to 1, need to add proper logic - line 1602: // FIXME need to confirm the MR2/MR4 or MR4/MR2 sequence from rtl team? no mention on spec - line 1871: //FIXME anything needs to be added? - line 1951: // //FIXME need to add - line 1954: //FIXME as per jedec spec, what is odd/even bytes in read data? - line 2038: updated_data[(i*32)+:32] = $urandom(); //FIXME all channels must generate diff set of random data. Also, every read to the same location will return different rand value within channel. shall seed it with addresss? think further about seeding.. - line 2074: rand_data[(i*32)+:32] = $urandom(); //FIXME all channels must generate diff set of random data. shall seed it with addresss? think further about seeding.. - line 2283: else begin /*Initialization Sequence*/ //FIXME need to write logic to detect initialization sequence - line 2387: //valid_row_cmd = 1; // FIXME do we need to consider it as valid command - line 2517: else `hbm_fatal(TAG, $sformatf("Sending ACTIVATE command to open Row is invalid in LEGACY Mode. %0s", get_page_info(page_addr))) //FIXME does this check required? - line 2522: //else `hbm_warning(TAG, $sformatf("Sending PRECHARGE command to closed Row is invalid. %0s", get_page_info(page_addr))) //FIXME does this check required? - line 2526: //else `hbm_warning(TAG, $sformatf("Sending PRECHARGE_ALL command while none of the Rows are opened is invalid. %0s", get_page_info(page_addr))) //FIXME does this check required? hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/xcelium/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.gen/sources_1/ip/pcie_bridge_rc/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh (2 lines): - line 4: logic [8:0] wadr; // FIXME hack should be 8 bits - line 9: logic [8:0] radr; // FIXME hack should be 8 bits hdk/common/verif/models/sh_bfm/sh_bfm.sv (2 lines): - line 477: /* TODO: Use the code below once plusarg support is enabled - line 604: // TODO: Connect up DDR stats interfaces if needed hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/vcs/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/questa/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/vcs/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/modelsim/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/xsim/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.gen/sources_1/ip/pcie_bridge_ep/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh (2 lines): - line 4: logic [8:0] wadr; // FIXME hack should be 8 bits - line 9: logic [8:0] radr; // FIXME hack should be 8 bits hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_2x2/ip/cl_axi_sc_2x2_smartconnect_0_0/xtlm/smartconnect_xtlm.h (2 lines): - line 82: // TODO: Pluralize... - line 90: // TODO: delete - should not be required: hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/modelsim/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/verif/tb/sv/dma_classes.sv (2 lines): - line 22: //TODO: - line 1278: // - Randomly ring doorbell (currently fixed at 50% chance, FIXME -- Make this parameterizable) hdk/common/ip/cl_ip/cl_ip.ip_user_files/mem_init_files/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/ipstatic/hdl/verilog/dma_pcie_mi_64Bx256_32Bwe_ram_if.svh (2 lines): - line 4: logic [8:0] wadr; // FIXME hack should be 8 bits - line 9: logic [8:0] radr; // FIXME hack should be 8 bits hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/riviera/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/xsim/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/questa/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_1x1/ip/cl_axi_sc_1x1_smartconnect_0_0/xtlm/smartconnect_xtlm.h (2 lines): - line 82: // TODO: Pluralize... - line 90: // TODO: delete - should not be required: hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_2x2/ip/cl_axi_sc_2x2_smartconnect_0_0/xtlm/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/activehdl/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/activehdl/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/xcelium/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/riviera/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_1x1/ip/cl_axi_sc_1x1_smartconnect_0_0/xtlm/smartconnect.cxx (2 lines): - line 73: // TODO: need the component name of the IP instance - line 75: // TODO: acquire SC config from file handoff (sc_xtlm.rtd file) hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/activehdl/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/modelsim/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.gen/sources_1/ip/cl_hbm/sysc/src/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/mem_init_files/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/modelsim/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/mem_init_files/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_2x2/ip/cl_axi_sc_2x2_smartconnect_0_0/xtlm/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/xsim/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/questa/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.gen/sources_1/bd/cl_axi_sc_1x1/ip/cl_axi_sc_1x1_smartconnect_0_0/xtlm/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/vcs/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/xcelium/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/xcelium/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/questa/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name sdk/userspace/fpga_libs/fpga_dma/fpga_dma_utils.c (1 line): - line 72: /* TODO: this isn't really the right error code. */ hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/modelsim/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/riviera/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/vcs/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/verif/models/sh_bfm/axil_bfm.sv (1 line): - line 64: /* TODO: Use the code below once plusarg support is enabled hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/activehdl/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_hbm/xcelium/hbm_fmodel_shared_memory.cxx (1 line): - line 308: // TODO: DDR_BUFFER_ALIGNMENT 0x1000 (4096) this is declared in runtime shim. hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/questa/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/vcs/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/xsim/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/activehdl/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/xsim/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_1x1/riviera/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts/cl_axi_sc_2x2/riviera/smartconnect_xtlm.cxx (1 line): - line 273: // TODO: change iterator name hdk/common/shell_stable/build/scripts/synth_cl_footer.tcl (1 line): - line 29: # TODO: Remove this once we discover why DDR is not calibrated by default hdk/common/verif/tb/scripts/Makefile.header.inc (1 line): - line 44: # TODO: Come back to this