in runtime/vm/simulator_arm.cc [1532:2129]
DART_FORCE_INLINE void Simulator::DecodeType01(Instr* instr) {
if (!instr->IsDataProcessing()) {
// miscellaneous, multiply, sync primitives, extra loads and stores.
if (instr->IsMiscellaneous()) {
switch (instr->Bits(4, 3)) {
case 1: {
if (instr->Bits(21, 2) == 0x3) {
// Format(instr, "clz'cond 'rd, 'rm");
Register rm = instr->RmField();
Register rd = instr->RdField();
int32_t rm_val = get_register(rm);
int32_t rd_val = 0;
if (rm_val != 0) {
while (rm_val > 0) {
rd_val++;
rm_val <<= 1;
}
} else {
rd_val = 32;
}
set_register(rd, rd_val);
} else {
ASSERT(instr->Bits(21, 2) == 0x1);
// Format(instr, "bx'cond 'rm");
Register rm = instr->RmField();
int32_t rm_val = get_register(rm);
set_pc(rm_val);
}
break;
}
case 3: {
ASSERT(instr->Bits(21, 2) == 0x1);
// Format(instr, "blx'cond 'rm");
Register rm = instr->RmField();
int32_t rm_val = get_register(rm);
intptr_t pc = get_pc();
set_register(LR, pc + Instr::kInstrSize);
set_pc(rm_val);
break;
}
case 7: {
if ((instr->Bits(21, 2) == 0x1) && (instr->ConditionField() == AL)) {
// Format(instr, "bkpt #'imm12_4");
SimulatorDebugger dbg(this);
int32_t imm = instr->BkptField();
char buffer[32];
snprintf(buffer, sizeof(buffer), "bkpt #0x%x", imm);
set_pc(get_pc() + Instr::kInstrSize);
dbg.Stop(instr, buffer);
} else {
// Format(instr, "smc'cond");
UnimplementedInstruction(instr);
}
break;
}
default: {
UnimplementedInstruction(instr);
break;
}
}
} else if (instr->IsMultiplyOrSyncPrimitive()) {
if (instr->Bit(24) == 0) {
// multiply instructions.
Register rn = instr->RnField();
Register rd = instr->RdField();
Register rs = instr->RsField();
Register rm = instr->RmField();
uint32_t rm_val = get_register(rm);
uint32_t rs_val = get_register(rs);
uint32_t rd_val = 0;
switch (instr->Bits(21, 3)) {
case 1:
// Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
// Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
case 3: {
// Registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
// Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
rd_val = get_register(rd);
FALL_THROUGH;
}
case 0: {
// Registers rd, rn, rm are encoded as rn, rm, rs.
// Format(instr, "mul'cond's 'rn, 'rm, 'rs");
uint32_t alu_out = rm_val * rs_val;
if (instr->Bits(21, 3) == 3) { // mls
alu_out = -alu_out;
}
alu_out += rd_val;
set_register(rn, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
}
break;
}
case 4:
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
// Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs");
case 6: {
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
// Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs");
int64_t result;
if (instr->Bits(21, 3) == 4) { // umull
uint64_t left_op = static_cast<uint32_t>(rm_val);
uint64_t right_op = static_cast<uint32_t>(rs_val);
result = left_op * right_op; // Unsigned multiplication.
} else { // smull
int64_t left_op = static_cast<int32_t>(rm_val);
int64_t right_op = static_cast<int32_t>(rs_val);
result = left_op * right_op; // Signed multiplication.
}
int32_t hi_res = Utils::High32Bits(result);
int32_t lo_res = Utils::Low32Bits(result);
set_register(rd, lo_res);
set_register(rn, hi_res);
if (instr->HasS()) {
if (lo_res != 0) {
// Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
hi_res |= 1;
}
ASSERT((result == 0) == (hi_res == 0)); // Z bit
ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit
SetNZFlags(hi_res);
}
break;
}
case 2:
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
// Format(instr, "umaal'cond's 'rd, 'rn, 'rm, 'rs");
FALL_THROUGH;
case 5:
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
// Format(instr, "umlal'cond's 'rd, 'rn, 'rm, 'rs");
FALL_THROUGH;
case 7: {
// Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
// Format(instr, "smlal'cond's 'rd, 'rn, 'rm, 'rs");
int32_t rd_lo_val = get_register(rd);
int32_t rd_hi_val = get_register(rn);
uint32_t accum_lo = static_cast<uint32_t>(rd_lo_val);
int32_t accum_hi = static_cast<int32_t>(rd_hi_val);
int64_t accum = Utils::LowHighTo64Bits(accum_lo, accum_hi);
int64_t result;
if (instr->Bits(21, 3) == 5) { // umlal
uint64_t left_op = static_cast<uint32_t>(rm_val);
uint64_t right_op = static_cast<uint32_t>(rs_val);
result = accum + left_op * right_op; // Unsigned multiplication.
} else if (instr->Bits(21, 3) == 7) { // smlal
int64_t left_op = static_cast<int32_t>(rm_val);
int64_t right_op = static_cast<int32_t>(rs_val);
result = accum + left_op * right_op; // Signed multiplication.
} else {
ASSERT(instr->Bits(21, 3) == 2); // umaal
ASSERT(!instr->HasS());
uint64_t left_op = static_cast<uint32_t>(rm_val);
uint64_t right_op = static_cast<uint32_t>(rs_val);
result = left_op * right_op + // Unsigned multiplication.
static_cast<uint32_t>(rd_lo_val) +
static_cast<uint32_t>(rd_hi_val);
}
int32_t hi_res = Utils::High32Bits(result);
int32_t lo_res = Utils::Low32Bits(result);
set_register(rd, lo_res);
set_register(rn, hi_res);
if (instr->HasS()) {
if (lo_res != 0) {
// Collapse bits 0..31 into bit 32 so that 32-bit Z check works.
hi_res |= 1;
}
ASSERT((result == 0) == (hi_res == 0)); // Z bit
ASSERT(((result & (1LL << 63)) != 0) == (hi_res < 0)); // N bit
SetNZFlags(hi_res);
}
break;
}
default: {
UnimplementedInstruction(instr);
break;
}
}
} else {
// synchronization primitives
Register rd = instr->RdField();
Register rn = instr->RnField();
uword addr = get_register(rn);
switch (instr->Bits(20, 4)) {
case 8: {
// Format(instr, "strex'cond 'rd, 'rm, ['rn]");
if (IsIllegalAddress(addr)) {
HandleIllegalAccess(addr, instr);
} else {
Register rm = instr->RmField();
set_register(rd, WriteExclusiveW(addr, get_register(rm), instr));
}
break;
}
case 9: {
// Format(instr, "ldrex'cond 'rd, ['rn]");
if (IsIllegalAddress(addr)) {
HandleIllegalAccess(addr, instr);
} else {
set_register(rd, ReadExclusiveW(addr, instr));
}
break;
}
default: {
UnimplementedInstruction(instr);
break;
}
}
}
} else if (instr->Bit(25) == 1) {
// 16-bit immediate loads, msr (immediate), and hints
switch (instr->Bits(20, 5)) {
case 16:
case 20: {
uint16_t imm16 = instr->MovwField();
Register rd = instr->RdField();
if (instr->Bit(22) == 0) {
// Format(instr, "movw'cond 'rd, #'imm4_12");
set_register(rd, imm16);
} else {
// Format(instr, "movt'cond 'rd, #'imm4_12");
set_register(rd, (get_register(rd) & 0xffff) | (imm16 << 16));
}
break;
}
case 18: {
if ((instr->Bits(16, 4) == 0) && (instr->Bits(0, 8) == 0)) {
// Format(instr, "nop'cond");
} else {
UnimplementedInstruction(instr);
}
break;
}
default: {
UnimplementedInstruction(instr);
break;
}
}
} else {
// extra load/store instructions
Register rd = instr->RdField();
Register rn = instr->RnField();
int32_t rn_val = get_register(rn);
uword addr = 0;
bool write_back = false;
if (instr->Bit(22) == 0) {
Register rm = instr->RmField();
int32_t rm_val = get_register(rm);
switch (instr->PUField()) {
case 0: {
// Format(instr, "'memop'cond'x 'rd2, ['rn], -'rm");
ASSERT(!instr->HasW());
addr = rn_val;
rn_val -= rm_val;
write_back = true;
break;
}
case 1: {
// Format(instr, "'memop'cond'x 'rd2, ['rn], +'rm");
ASSERT(!instr->HasW());
addr = rn_val;
rn_val += rm_val;
write_back = true;
break;
}
case 2: {
// Format(instr, "'memop'cond'x 'rd2, ['rn, -'rm]'w");
rn_val -= rm_val;
addr = rn_val;
write_back = instr->HasW();
break;
}
case 3: {
// Format(instr, "'memop'cond'x 'rd2, ['rn, +'rm]'w");
rn_val += rm_val;
addr = rn_val;
write_back = instr->HasW();
break;
}
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
} else {
int32_t imm_val = (instr->ImmedHField() << 4) | instr->ImmedLField();
switch (instr->PUField()) {
case 0: {
// Format(instr, "'memop'cond'x 'rd2, ['rn], #-'off8");
ASSERT(!instr->HasW());
addr = rn_val;
rn_val -= imm_val;
write_back = true;
break;
}
case 1: {
// Format(instr, "'memop'cond'x 'rd2, ['rn], #+'off8");
ASSERT(!instr->HasW());
addr = rn_val;
rn_val += imm_val;
write_back = true;
break;
}
case 2: {
// Format(instr, "'memop'cond'x 'rd2, ['rn, #-'off8]'w");
rn_val -= imm_val;
addr = rn_val;
write_back = instr->HasW();
break;
}
case 3: {
// Format(instr, "'memop'cond'x 'rd2, ['rn, #+'off8]'w");
rn_val += imm_val;
addr = rn_val;
write_back = instr->HasW();
break;
}
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
}
if (IsIllegalAddress(addr)) {
HandleIllegalAccess(addr, instr);
} else {
if (write_back) {
ASSERT(rd != rn); // Unpredictable.
set_register(rn, rn_val);
}
if (!instr->HasSign()) {
if (instr->HasL()) {
uint16_t val = ReadHU(addr, instr);
set_register(rd, val);
} else {
uint16_t val = get_register(rd);
WriteH(addr, val, instr);
}
} else if (instr->HasL()) {
if (instr->HasH()) {
int16_t val = ReadH(addr, instr);
set_register(rd, val);
} else {
int8_t val = ReadB(addr);
set_register(rd, val);
}
} else if ((rd & 1) == 0) {
Register rd1 = static_cast<Register>(rd | 1);
ASSERT(rd1 < kNumberOfCpuRegisters);
if (instr->HasH()) {
int32_t val_low = get_register(rd);
int32_t val_high = get_register(rd1);
WriteW(addr, val_low, instr);
WriteW(addr + 4, val_high, instr);
} else {
int32_t val_low = ReadW(addr, instr);
int32_t val_high = ReadW(addr + 4, instr);
set_register(rd, val_low);
set_register(rd1, val_high);
}
} else {
UnimplementedInstruction(instr);
}
}
}
} else {
Register rd = instr->RdField();
Register rn = instr->RnField();
uint32_t rn_val = get_register(rn);
uint32_t shifter_operand = 0;
bool shifter_carry_out = 0;
if (instr->TypeField() == 0) {
shifter_operand = GetShiftRm(instr, &shifter_carry_out);
} else {
ASSERT(instr->TypeField() == 1);
shifter_operand = GetImm(instr, &shifter_carry_out);
}
uint32_t carry_in;
uint32_t alu_out;
switch (instr->OpcodeField()) {
case AND: {
// Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "and'cond's 'rd, 'rn, 'imm");
alu_out = rn_val & shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case EOR: {
// Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "eor'cond's 'rd, 'rn, 'imm");
alu_out = rn_val ^ shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case SUB: {
// Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "sub'cond's 'rd, 'rn, 'imm");
alu_out = rn_val - shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, ~shifter_operand, 1));
SetVFlag(OverflowFrom(rn_val, ~shifter_operand, 1));
}
break;
}
case RSB: {
// Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
alu_out = shifter_operand - rn_val;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(shifter_operand, ~rn_val, 1));
SetVFlag(OverflowFrom(shifter_operand, ~rn_val, 1));
}
break;
}
case ADD: {
// Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "add'cond's 'rd, 'rn, 'imm");
alu_out = rn_val + shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand, 0));
SetVFlag(OverflowFrom(rn_val, shifter_operand, 0));
}
break;
}
case ADC: {
// Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "adc'cond's 'rd, 'rn, 'imm");
carry_in = c_flag_ ? 1 : 0;
alu_out = rn_val + shifter_operand + carry_in;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand, carry_in));
SetVFlag(OverflowFrom(rn_val, shifter_operand, carry_in));
}
break;
}
case SBC: {
// Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
carry_in = c_flag_ ? 1 : 0;
alu_out = rn_val + ~shifter_operand + carry_in;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, ~shifter_operand, carry_in));
SetVFlag(OverflowFrom(rn_val, ~shifter_operand, carry_in));
}
break;
}
case RSC: {
// Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
carry_in = c_flag_ ? 1 : 0;
alu_out = shifter_operand + ~rn_val + carry_in;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(shifter_operand, ~rn_val, carry_in));
SetVFlag(OverflowFrom(shifter_operand, ~rn_val, carry_in));
}
break;
}
case TST: {
if (instr->HasS()) {
// Format(instr, "tst'cond 'rn, 'shift_rm");
// Format(instr, "tst'cond 'rn, 'imm");
alu_out = rn_val & shifter_operand;
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
} else {
UnimplementedInstruction(instr);
}
break;
}
case TEQ: {
if (instr->HasS()) {
// Format(instr, "teq'cond 'rn, 'shift_rm");
// Format(instr, "teq'cond 'rn, 'imm");
alu_out = rn_val ^ shifter_operand;
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
} else {
UnimplementedInstruction(instr);
}
break;
}
case CMP: {
if (instr->HasS()) {
// Format(instr, "cmp'cond 'rn, 'shift_rm");
// Format(instr, "cmp'cond 'rn, 'imm");
alu_out = rn_val - shifter_operand;
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, ~shifter_operand, 1));
SetVFlag(OverflowFrom(rn_val, ~shifter_operand, 1));
} else {
UnimplementedInstruction(instr);
}
break;
}
case CMN: {
if (instr->HasS()) {
// Format(instr, "cmn'cond 'rn, 'shift_rm");
// Format(instr, "cmn'cond 'rn, 'imm");
alu_out = rn_val + shifter_operand;
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand, 0));
SetVFlag(OverflowFrom(rn_val, shifter_operand, 0));
} else {
UnimplementedInstruction(instr);
}
break;
}
case ORR: {
// Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "orr'cond's 'rd, 'rn, 'imm");
alu_out = rn_val | shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case MOV: {
// Format(instr, "mov'cond's 'rd, 'shift_rm");
// Format(instr, "mov'cond's 'rd, 'imm");
alu_out = shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case BIC: {
// Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "bic'cond's 'rd, 'rn, 'imm");
alu_out = rn_val & ~shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case MVN: {
// Format(instr, "mvn'cond's 'rd, 'shift_rm");
// Format(instr, "mvn'cond's 'rd, 'imm");
alu_out = ~shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
default: {
UNREACHABLE();
break;
}
}
}
}