in src/cmd/compile/internal/ssa/rewritegeneric.go [12681:14019]
func rewriteValuegeneric_OpMove(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
config := b.Func.Config
// match: (Move {t} [n] dst1 src mem:(Zero {t} [n] dst2 _))
// cond: isSamePtr(src, dst2)
// result: (Zero {t} [n] dst1 mem)
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src := v_1
mem := v_2
if mem.Op != OpZero || auxIntToInt64(mem.AuxInt) != n || auxToType(mem.Aux) != t {
break
}
dst2 := mem.Args[0]
if !(isSamePtr(src, dst2)) {
break
}
v.reset(OpZero)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v.AddArg2(dst1, mem)
return true
}
// match: (Move {t} [n] dst1 src mem:(VarDef (Zero {t} [n] dst0 _)))
// cond: isSamePtr(src, dst0)
// result: (Zero {t} [n] dst1 mem)
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpZero || auxIntToInt64(mem_0.AuxInt) != n || auxToType(mem_0.Aux) != t {
break
}
dst0 := mem_0.Args[0]
if !(isSamePtr(src, dst0)) {
break
}
v.reset(OpZero)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v.AddArg2(dst1, mem)
return true
}
// match: (Move {t} [n] dst (Addr {sym} (SB)) mem)
// cond: symIsROZero(sym)
// result: (Zero {t} [n] dst mem)
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst := v_0
if v_1.Op != OpAddr {
break
}
sym := auxToSym(v_1.Aux)
v_1_0 := v_1.Args[0]
if v_1_0.Op != OpSB {
break
}
mem := v_2
if !(symIsROZero(sym)) {
break
}
v.reset(OpZero)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v.AddArg2(dst, mem)
return true
}
// match: (Move {t1} [n] dst1 src1 store:(Store {t2} op:(OffPtr [o2] dst2) _ mem))
// cond: isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2 + t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)
// result: (Move {t1} [n] dst1 src1 mem)
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst1 := v_0
src1 := v_1
store := v_2
if store.Op != OpStore {
break
}
t2 := auxToType(store.Aux)
mem := store.Args[2]
op := store.Args[0]
if op.Op != OpOffPtr {
break
}
o2 := auxIntToInt64(op.AuxInt)
dst2 := op.Args[0]
if !(isSamePtr(dst1, dst2) && store.Uses == 1 && n >= o2+t2.Size() && disjoint(src1, n, op, t2.Size()) && clobber(store)) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t1)
v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 move:(Move {t} [n] dst2 _ mem))
// cond: move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)
// result: (Move {t} [n] dst1 src1 mem)
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src1 := v_1
move := v_2
if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t {
break
}
mem := move.Args[2]
dst2 := move.Args[0]
if !(move.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move)) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} move:(Move {t} [n] dst2 _ mem)))
// cond: move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)
// result: (Move {t} [n] dst1 src1 (VarDef {x} mem))
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src1 := v_1
vardef := v_2
if vardef.Op != OpVarDef {
break
}
x := auxToSym(vardef.Aux)
move := vardef.Args[0]
if move.Op != OpMove || auxIntToInt64(move.AuxInt) != n || auxToType(move.Aux) != t {
break
}
mem := move.Args[2]
dst2 := move.Args[0]
if !(move.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(move, vardef)) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = symToAux(x)
v0.AddArg(mem)
v.AddArg3(dst1, src1, v0)
return true
}
// match: (Move {t} [n] dst1 src1 zero:(Zero {t} [n] dst2 mem))
// cond: zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)
// result: (Move {t} [n] dst1 src1 mem)
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src1 := v_1
zero := v_2
if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t {
break
}
mem := zero.Args[1]
dst2 := zero.Args[0]
if !(zero.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero)) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v.AddArg3(dst1, src1, mem)
return true
}
// match: (Move {t} [n] dst1 src1 vardef:(VarDef {x} zero:(Zero {t} [n] dst2 mem)))
// cond: zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)
// result: (Move {t} [n] dst1 src1 (VarDef {x} mem))
for {
n := auxIntToInt64(v.AuxInt)
t := auxToType(v.Aux)
dst1 := v_0
src1 := v_1
vardef := v_2
if vardef.Op != OpVarDef {
break
}
x := auxToSym(vardef.Aux)
zero := vardef.Args[0]
if zero.Op != OpZero || auxIntToInt64(zero.AuxInt) != n || auxToType(zero.Aux) != t {
break
}
mem := zero.Args[1]
dst2 := zero.Args[0]
if !(zero.Uses == 1 && vardef.Uses == 1 && isSamePtr(dst1, dst2) && disjoint(src1, n, dst2, n) && clobber(zero, vardef)) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(n)
v.Aux = typeToAux(t)
v0 := b.NewValue0(v.Pos, OpVarDef, types.TypeMem)
v0.Aux = symToAux(x)
v0.AddArg(mem)
v.AddArg3(dst1, src1, v0)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [0] p3) d2 _)))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [0] dst) d2 mem))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
op2 := mem.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
d2 := mem_2.Args[1]
op3 := mem_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
if auxIntToInt64(op3.AuxInt) != 0 {
break
}
p3 := op3.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(0)
v2.AddArg(dst)
v1.AddArg3(v2, d2, mem)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [0] p4) d3 _))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [0] dst) d3 mem)))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
op2 := mem.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
_ = mem_2.Args[2]
op3 := mem_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
o3 := auxIntToInt64(op3.AuxInt)
p3 := op3.Args[0]
d2 := mem_2.Args[1]
mem_2_2 := mem_2.Args[2]
if mem_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_2_2.Aux)
d3 := mem_2_2.Args[1]
op4 := mem_2_2.Args[0]
if op4.Op != OpOffPtr {
break
}
tt4 := op4.Type
if auxIntToInt64(op4.AuxInt) != 0 {
break
}
p4 := op4.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(0)
v4.AddArg(dst)
v3.AddArg3(v4, d3, mem)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [o4] p4) d3 (Store {t5} op5:(OffPtr <tt5> [0] p5) d4 _)))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Store {t5} (OffPtr <tt5> [0] dst) d4 mem))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
op2 := mem.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
_ = mem_2.Args[2]
op3 := mem_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
o3 := auxIntToInt64(op3.AuxInt)
p3 := op3.Args[0]
d2 := mem_2.Args[1]
mem_2_2 := mem_2.Args[2]
if mem_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_2_2.Aux)
_ = mem_2_2.Args[2]
op4 := mem_2_2.Args[0]
if op4.Op != OpOffPtr {
break
}
tt4 := op4.Type
o4 := auxIntToInt64(op4.AuxInt)
p4 := op4.Args[0]
d3 := mem_2_2.Args[1]
mem_2_2_2 := mem_2_2.Args[2]
if mem_2_2_2.Op != OpStore {
break
}
t5 := auxToType(mem_2_2_2.Aux)
d4 := mem_2_2_2.Args[1]
op5 := mem_2_2_2.Args[0]
if op5.Op != OpOffPtr {
break
}
tt5 := op5.Type
if auxIntToInt64(op5.AuxInt) != 0 {
break
}
p5 := op5.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = typeToAux(t5)
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = int64ToAuxInt(0)
v6.AddArg(dst)
v5.AddArg3(v6, d4, mem)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [0] p3) d2 _))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size() + t3.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [0] dst) d2 mem))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
op2 := mem_0.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
d2 := mem_0_2.Args[1]
op3 := mem_0_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
if auxIntToInt64(op3.AuxInt) != 0 {
break
}
p3 := op3.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && o2 == t3.Size() && n == t2.Size()+t3.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(0)
v2.AddArg(dst)
v1.AddArg3(v2, d2, mem)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [0] p4) d3 _)))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [0] dst) d3 mem)))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
op2 := mem_0.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
_ = mem_0_2.Args[2]
op3 := mem_0_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
o3 := auxIntToInt64(op3.AuxInt)
p3 := op3.Args[0]
d2 := mem_0_2.Args[1]
mem_0_2_2 := mem_0_2.Args[2]
if mem_0_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_0_2_2.Aux)
d3 := mem_0_2_2.Args[1]
op4 := mem_0_2_2.Args[0]
if op4.Op != OpOffPtr {
break
}
tt4 := op4.Type
if auxIntToInt64(op4.AuxInt) != 0 {
break
}
p4 := op4.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && o3 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(0)
v4.AddArg(dst)
v3.AddArg3(v4, d3, mem)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Store {t3} op3:(OffPtr <tt3> [o3] p3) d2 (Store {t4} op4:(OffPtr <tt4> [o4] p4) d3 (Store {t5} op5:(OffPtr <tt5> [0] p5) d4 _))))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size() + t3.Size() + t4.Size() + t5.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Store {t5} (OffPtr <tt5> [0] dst) d4 mem))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
op2 := mem_0.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
_ = mem_0_2.Args[2]
op3 := mem_0_2.Args[0]
if op3.Op != OpOffPtr {
break
}
tt3 := op3.Type
o3 := auxIntToInt64(op3.AuxInt)
p3 := op3.Args[0]
d2 := mem_0_2.Args[1]
mem_0_2_2 := mem_0_2.Args[2]
if mem_0_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_0_2_2.Aux)
_ = mem_0_2_2.Args[2]
op4 := mem_0_2_2.Args[0]
if op4.Op != OpOffPtr {
break
}
tt4 := op4.Type
o4 := auxIntToInt64(op4.AuxInt)
p4 := op4.Args[0]
d3 := mem_0_2_2.Args[1]
mem_0_2_2_2 := mem_0_2_2.Args[2]
if mem_0_2_2_2.Op != OpStore {
break
}
t5 := auxToType(mem_0_2_2_2.Aux)
d4 := mem_0_2_2_2.Args[1]
op5 := mem_0_2_2_2.Args[0]
if op5.Op != OpOffPtr {
break
}
tt5 := op5.Type
if auxIntToInt64(op5.AuxInt) != 0 {
break
}
p5 := op5.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && o4 == t5.Size() && o3-o4 == t4.Size() && o2-o3 == t3.Size() && n == t2.Size()+t3.Size()+t4.Size()+t5.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = typeToAux(t5)
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = int64ToAuxInt(0)
v6.AddArg(dst)
v5.AddArg3(v6, d4, mem)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Zero {t3} [n] p3 _)))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Zero {t1} [n] dst mem))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
op2 := mem.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpZero || auxIntToInt64(mem_2.AuxInt) != n {
break
}
t3 := auxToType(mem_2.Aux)
p3 := mem_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = int64ToAuxInt(n)
v1.Aux = typeToAux(t1)
v1.AddArg2(dst, mem)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Zero {t4} [n] p4 _))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Zero {t1} [n] dst mem)))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
mem_0 := mem.Args[0]
if mem_0.Op != OpOffPtr {
break
}
tt2 := mem_0.Type
o2 := auxIntToInt64(mem_0.AuxInt)
p2 := mem_0.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
_ = mem_2.Args[2]
mem_2_0 := mem_2.Args[0]
if mem_2_0.Op != OpOffPtr {
break
}
tt3 := mem_2_0.Type
o3 := auxIntToInt64(mem_2_0.AuxInt)
p3 := mem_2_0.Args[0]
d2 := mem_2.Args[1]
mem_2_2 := mem_2.Args[2]
if mem_2_2.Op != OpZero || auxIntToInt64(mem_2_2.AuxInt) != n {
break
}
t4 := auxToType(mem_2_2.Aux)
p4 := mem_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v3.AuxInt = int64ToAuxInt(n)
v3.Aux = typeToAux(t1)
v3.AddArg2(dst, mem)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Zero {t5} [n] p5 _)))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Zero {t1} [n] dst mem))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
mem_0 := mem.Args[0]
if mem_0.Op != OpOffPtr {
break
}
tt2 := mem_0.Type
o2 := auxIntToInt64(mem_0.AuxInt)
p2 := mem_0.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
_ = mem_2.Args[2]
mem_2_0 := mem_2.Args[0]
if mem_2_0.Op != OpOffPtr {
break
}
tt3 := mem_2_0.Type
o3 := auxIntToInt64(mem_2_0.AuxInt)
p3 := mem_2_0.Args[0]
d2 := mem_2.Args[1]
mem_2_2 := mem_2.Args[2]
if mem_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_2_2.Aux)
_ = mem_2_2.Args[2]
mem_2_2_0 := mem_2_2.Args[0]
if mem_2_2_0.Op != OpOffPtr {
break
}
tt4 := mem_2_2_0.Type
o4 := auxIntToInt64(mem_2_2_0.AuxInt)
p4 := mem_2_2_0.Args[0]
d3 := mem_2_2.Args[1]
mem_2_2_2 := mem_2_2.Args[2]
if mem_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2.AuxInt) != n {
break
}
t5 := auxToType(mem_2_2_2.Aux)
p5 := mem_2_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v5.AuxInt = int64ToAuxInt(n)
v5.Aux = typeToAux(t1)
v5.AddArg2(dst, mem)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Store {t5} (OffPtr <tt5> [o5] p5) d4 (Zero {t6} [n] p6 _))))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Store {t5} (OffPtr <tt5> [o5] dst) d4 (Zero {t1} [n] dst mem)))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpStore {
break
}
t2 := auxToType(mem.Aux)
_ = mem.Args[2]
mem_0 := mem.Args[0]
if mem_0.Op != OpOffPtr {
break
}
tt2 := mem_0.Type
o2 := auxIntToInt64(mem_0.AuxInt)
p2 := mem_0.Args[0]
d1 := mem.Args[1]
mem_2 := mem.Args[2]
if mem_2.Op != OpStore {
break
}
t3 := auxToType(mem_2.Aux)
_ = mem_2.Args[2]
mem_2_0 := mem_2.Args[0]
if mem_2_0.Op != OpOffPtr {
break
}
tt3 := mem_2_0.Type
o3 := auxIntToInt64(mem_2_0.AuxInt)
p3 := mem_2_0.Args[0]
d2 := mem_2.Args[1]
mem_2_2 := mem_2.Args[2]
if mem_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_2_2.Aux)
_ = mem_2_2.Args[2]
mem_2_2_0 := mem_2_2.Args[0]
if mem_2_2_0.Op != OpOffPtr {
break
}
tt4 := mem_2_2_0.Type
o4 := auxIntToInt64(mem_2_2_0.AuxInt)
p4 := mem_2_2_0.Args[0]
d3 := mem_2_2.Args[1]
mem_2_2_2 := mem_2_2.Args[2]
if mem_2_2_2.Op != OpStore {
break
}
t5 := auxToType(mem_2_2_2.Aux)
_ = mem_2_2_2.Args[2]
mem_2_2_2_0 := mem_2_2_2.Args[0]
if mem_2_2_2_0.Op != OpOffPtr {
break
}
tt5 := mem_2_2_2_0.Type
o5 := auxIntToInt64(mem_2_2_2_0.AuxInt)
p5 := mem_2_2_2_0.Args[0]
d4 := mem_2_2_2.Args[1]
mem_2_2_2_2 := mem_2_2_2.Args[2]
if mem_2_2_2_2.Op != OpZero || auxIntToInt64(mem_2_2_2_2.AuxInt) != n {
break
}
t6 := auxToType(mem_2_2_2_2.Aux)
p6 := mem_2_2_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = typeToAux(t5)
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = int64ToAuxInt(o5)
v6.AddArg(dst)
v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v7.AuxInt = int64ToAuxInt(n)
v7.Aux = typeToAux(t1)
v7.AddArg2(dst, mem)
v5.AddArg3(v6, d4, v7)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} op2:(OffPtr <tt2> [o2] p2) d1 (Zero {t3} [n] p3 _))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2 + t2.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Zero {t1} [n] dst mem))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
op2 := mem_0.Args[0]
if op2.Op != OpOffPtr {
break
}
tt2 := op2.Type
o2 := auxIntToInt64(op2.AuxInt)
p2 := op2.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpZero || auxIntToInt64(mem_0_2.AuxInt) != n {
break
}
t3 := auxToType(mem_0_2.Aux)
p3 := mem_0_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && registerizable(b, t2) && n >= o2+t2.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v1.AuxInt = int64ToAuxInt(n)
v1.Aux = typeToAux(t1)
v1.AddArg2(dst, mem)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Zero {t4} [n] p4 _)))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2 + t2.Size() && n >= o3 + t3.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Zero {t1} [n] dst mem)))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
mem_0_0 := mem_0.Args[0]
if mem_0_0.Op != OpOffPtr {
break
}
tt2 := mem_0_0.Type
o2 := auxIntToInt64(mem_0_0.AuxInt)
p2 := mem_0_0.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
_ = mem_0_2.Args[2]
mem_0_2_0 := mem_0_2.Args[0]
if mem_0_2_0.Op != OpOffPtr {
break
}
tt3 := mem_0_2_0.Type
o3 := auxIntToInt64(mem_0_2_0.AuxInt)
p3 := mem_0_2_0.Args[0]
d2 := mem_0_2.Args[1]
mem_0_2_2 := mem_0_2.Args[2]
if mem_0_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2.AuxInt) != n {
break
}
t4 := auxToType(mem_0_2_2.Aux)
p4 := mem_0_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && n >= o2+t2.Size() && n >= o3+t3.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v3.AuxInt = int64ToAuxInt(n)
v3.Aux = typeToAux(t1)
v3.AddArg2(dst, mem)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Zero {t5} [n] p5 _))))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Zero {t1} [n] dst mem))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
mem_0_0 := mem_0.Args[0]
if mem_0_0.Op != OpOffPtr {
break
}
tt2 := mem_0_0.Type
o2 := auxIntToInt64(mem_0_0.AuxInt)
p2 := mem_0_0.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
_ = mem_0_2.Args[2]
mem_0_2_0 := mem_0_2.Args[0]
if mem_0_2_0.Op != OpOffPtr {
break
}
tt3 := mem_0_2_0.Type
o3 := auxIntToInt64(mem_0_2_0.AuxInt)
p3 := mem_0_2_0.Args[0]
d2 := mem_0_2.Args[1]
mem_0_2_2 := mem_0_2.Args[2]
if mem_0_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_0_2_2.Aux)
_ = mem_0_2_2.Args[2]
mem_0_2_2_0 := mem_0_2_2.Args[0]
if mem_0_2_2_0.Op != OpOffPtr {
break
}
tt4 := mem_0_2_2_0.Type
o4 := auxIntToInt64(mem_0_2_2_0.AuxInt)
p4 := mem_0_2_2_0.Args[0]
d3 := mem_0_2_2.Args[1]
mem_0_2_2_2 := mem_0_2_2.Args[2]
if mem_0_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2.AuxInt) != n {
break
}
t5 := auxToType(mem_0_2_2_2.Aux)
p5 := mem_0_2_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v5.AuxInt = int64ToAuxInt(n)
v5.Aux = typeToAux(t1)
v5.AddArg2(dst, mem)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [n] dst p1 mem:(VarDef (Store {t2} (OffPtr <tt2> [o2] p2) d1 (Store {t3} (OffPtr <tt3> [o3] p3) d2 (Store {t4} (OffPtr <tt4> [o4] p4) d3 (Store {t5} (OffPtr <tt5> [o5] p5) d4 (Zero {t6} [n] p6 _)))))))
// cond: isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2 + t2.Size() && n >= o3 + t3.Size() && n >= o4 + t4.Size() && n >= o5 + t5.Size()
// result: (Store {t2} (OffPtr <tt2> [o2] dst) d1 (Store {t3} (OffPtr <tt3> [o3] dst) d2 (Store {t4} (OffPtr <tt4> [o4] dst) d3 (Store {t5} (OffPtr <tt5> [o5] dst) d4 (Zero {t1} [n] dst mem)))))
for {
n := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
p1 := v_1
mem := v_2
if mem.Op != OpVarDef {
break
}
mem_0 := mem.Args[0]
if mem_0.Op != OpStore {
break
}
t2 := auxToType(mem_0.Aux)
_ = mem_0.Args[2]
mem_0_0 := mem_0.Args[0]
if mem_0_0.Op != OpOffPtr {
break
}
tt2 := mem_0_0.Type
o2 := auxIntToInt64(mem_0_0.AuxInt)
p2 := mem_0_0.Args[0]
d1 := mem_0.Args[1]
mem_0_2 := mem_0.Args[2]
if mem_0_2.Op != OpStore {
break
}
t3 := auxToType(mem_0_2.Aux)
_ = mem_0_2.Args[2]
mem_0_2_0 := mem_0_2.Args[0]
if mem_0_2_0.Op != OpOffPtr {
break
}
tt3 := mem_0_2_0.Type
o3 := auxIntToInt64(mem_0_2_0.AuxInt)
p3 := mem_0_2_0.Args[0]
d2 := mem_0_2.Args[1]
mem_0_2_2 := mem_0_2.Args[2]
if mem_0_2_2.Op != OpStore {
break
}
t4 := auxToType(mem_0_2_2.Aux)
_ = mem_0_2_2.Args[2]
mem_0_2_2_0 := mem_0_2_2.Args[0]
if mem_0_2_2_0.Op != OpOffPtr {
break
}
tt4 := mem_0_2_2_0.Type
o4 := auxIntToInt64(mem_0_2_2_0.AuxInt)
p4 := mem_0_2_2_0.Args[0]
d3 := mem_0_2_2.Args[1]
mem_0_2_2_2 := mem_0_2_2.Args[2]
if mem_0_2_2_2.Op != OpStore {
break
}
t5 := auxToType(mem_0_2_2_2.Aux)
_ = mem_0_2_2_2.Args[2]
mem_0_2_2_2_0 := mem_0_2_2_2.Args[0]
if mem_0_2_2_2_0.Op != OpOffPtr {
break
}
tt5 := mem_0_2_2_2_0.Type
o5 := auxIntToInt64(mem_0_2_2_2_0.AuxInt)
p5 := mem_0_2_2_2_0.Args[0]
d4 := mem_0_2_2_2.Args[1]
mem_0_2_2_2_2 := mem_0_2_2_2.Args[2]
if mem_0_2_2_2_2.Op != OpZero || auxIntToInt64(mem_0_2_2_2_2.AuxInt) != n {
break
}
t6 := auxToType(mem_0_2_2_2_2.Aux)
p6 := mem_0_2_2_2_2.Args[0]
if !(isSamePtr(p1, p2) && isSamePtr(p2, p3) && isSamePtr(p3, p4) && isSamePtr(p4, p5) && isSamePtr(p5, p6) && t2.Alignment() <= t1.Alignment() && t3.Alignment() <= t1.Alignment() && t4.Alignment() <= t1.Alignment() && t5.Alignment() <= t1.Alignment() && t6.Alignment() <= t1.Alignment() && registerizable(b, t2) && registerizable(b, t3) && registerizable(b, t4) && registerizable(b, t5) && n >= o2+t2.Size() && n >= o3+t3.Size() && n >= o4+t4.Size() && n >= o5+t5.Size()) {
break
}
v.reset(OpStore)
v.Aux = typeToAux(t2)
v0 := b.NewValue0(v.Pos, OpOffPtr, tt2)
v0.AuxInt = int64ToAuxInt(o2)
v0.AddArg(dst)
v1 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v1.Aux = typeToAux(t3)
v2 := b.NewValue0(v.Pos, OpOffPtr, tt3)
v2.AuxInt = int64ToAuxInt(o3)
v2.AddArg(dst)
v3 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v3.Aux = typeToAux(t4)
v4 := b.NewValue0(v.Pos, OpOffPtr, tt4)
v4.AuxInt = int64ToAuxInt(o4)
v4.AddArg(dst)
v5 := b.NewValue0(v.Pos, OpStore, types.TypeMem)
v5.Aux = typeToAux(t5)
v6 := b.NewValue0(v.Pos, OpOffPtr, tt5)
v6.AuxInt = int64ToAuxInt(o5)
v6.AddArg(dst)
v7 := b.NewValue0(v.Pos, OpZero, types.TypeMem)
v7.AuxInt = int64ToAuxInt(n)
v7.Aux = typeToAux(t1)
v7.AddArg2(dst, mem)
v5.AddArg3(v6, d4, v7)
v3.AddArg3(v4, d3, v5)
v1.AddArg3(v2, d2, v3)
v.AddArg3(v0, d1, v1)
return true
}
// match: (Move {t1} [s] dst tmp1 midmem:(Move {t2} [s] tmp2 src _))
// cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))
// result: (Move {t1} [s] dst src midmem)
for {
s := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
tmp1 := v_1
midmem := v_2
if midmem.Op != OpMove || auxIntToInt64(midmem.AuxInt) != s {
break
}
t2 := auxToType(midmem.Aux)
src := midmem.Args[1]
tmp2 := midmem.Args[0]
if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(s)
v.Aux = typeToAux(t1)
v.AddArg3(dst, src, midmem)
return true
}
// match: (Move {t1} [s] dst tmp1 midmem:(VarDef (Move {t2} [s] tmp2 src _)))
// cond: t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))
// result: (Move {t1} [s] dst src midmem)
for {
s := auxIntToInt64(v.AuxInt)
t1 := auxToType(v.Aux)
dst := v_0
tmp1 := v_1
midmem := v_2
if midmem.Op != OpVarDef {
break
}
midmem_0 := midmem.Args[0]
if midmem_0.Op != OpMove || auxIntToInt64(midmem_0.AuxInt) != s {
break
}
t2 := auxToType(midmem_0.Aux)
src := midmem_0.Args[1]
tmp2 := midmem_0.Args[0]
if !(t1.Compare(t2) == types.CMPeq && isSamePtr(tmp1, tmp2) && isStackPtr(src) && !isVolatile(src) && disjoint(src, s, tmp2, s) && (disjoint(src, s, dst, s) || isInlinableMemmove(dst, src, s, config))) {
break
}
v.reset(OpMove)
v.AuxInt = int64ToAuxInt(s)
v.Aux = typeToAux(t1)
v.AddArg3(dst, src, midmem)
return true
}
// match: (Move dst src mem)
// cond: isSamePtr(dst, src)
// result: mem
for {
dst := v_0
src := v_1
mem := v_2
if !(isSamePtr(dst, src)) {
break
}
v.copyOf(mem)
return true
}
return false
}