in src/cmd/compile/internal/ssa/rewriteAMD64.go [33764:35214]
func rewriteBlockAMD64(b *Block) bool {
switch b.Kind {
case BlockAMD64EQ:
// match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y))
// result: (UGE (BTL x y))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64SHLL {
continue
}
x := v_0_0.Args[1]
v_0_0_0 := v_0_0.Args[0]
if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 {
continue
}
y := v_0_1
v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags)
v0.AddArg2(x, y)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y))
// result: (UGE (BTQ x y))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64SHLQ {
continue
}
x := v_0_0.Args[1]
v_0_0_0 := v_0_0.Args[0]
if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 {
continue
}
y := v_0_1
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags)
v0.AddArg2(x, y)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTLconst [c] x))
// cond: isUint32PowerOfTwo(int64(c))
// result: (UGE (BTLconst [int8(log32(c))] x))
for b.Controls[0].Op == OpAMD64TESTLconst {
v_0 := b.Controls[0]
c := auxIntToInt32(v_0.AuxInt)
x := v_0.Args[0]
if !(isUint32PowerOfTwo(int64(c))) {
break
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log32(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
// match: (EQ (TESTQconst [c] x))
// cond: isUint64PowerOfTwo(int64(c))
// result: (UGE (BTQconst [int8(log32(c))] x))
for b.Controls[0].Op == OpAMD64TESTQconst {
v_0 := b.Controls[0]
c := auxIntToInt32(v_0.AuxInt)
x := v_0.Args[0]
if !(isUint64PowerOfTwo(int64(c))) {
break
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log32(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
// match: (EQ (TESTQ (MOVQconst [c]) x))
// cond: isUint64PowerOfTwo(c)
// result: (UGE (BTQconst [int8(log64(c))] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64MOVQconst {
continue
}
c := auxIntToInt64(v_0_0.AuxInt)
x := v_0_1
if !(isUint64PowerOfTwo(c)) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log64(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
// cond: z1==z2
// result: (UGE (BTQconst [63] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(63)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
// cond: z1==z2
// result: (UGE (BTQconst [31] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(31)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
// cond: z1==z2
// result: (UGE (BTQconst [0] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(0)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
// cond: z1==z2
// result: (UGE (BTLconst [0] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(0)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTQ z1:(SHRQconst [63] x) z2))
// cond: z1==z2
// result: (UGE (BTQconst [63] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
x := z1.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(63)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (TESTL z1:(SHRLconst [31] x) z2))
// cond: z1==z2
// result: (UGE (BTLconst [31] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
x := z1.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(31)
v0.AddArg(x)
b.resetWithControl(BlockAMD64UGE, v0)
return true
}
break
}
// match: (EQ (InvertFlags cmp) yes no)
// result: (EQ cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64EQ, cmp)
return true
}
// match: (EQ (FlagEQ) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
return true
}
// match: (EQ (FlagLT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (EQ (FlagLT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (EQ (FlagGT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (EQ (FlagGT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
case BlockAMD64GE:
// match: (GE (InvertFlags cmp) yes no)
// result: (LE cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64LE, cmp)
return true
}
// match: (GE (FlagEQ) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
return true
}
// match: (GE (FlagLT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (GE (FlagLT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (GE (FlagGT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (GE (FlagGT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
return true
}
case BlockAMD64GT:
// match: (GT (InvertFlags cmp) yes no)
// result: (LT cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64LT, cmp)
return true
}
// match: (GT (FlagEQ) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (GT (FlagLT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (GT (FlagLT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (GT (FlagGT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (GT (FlagGT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
return true
}
case BlockIf:
// match: (If (SETL cmp) yes no)
// result: (LT cmp yes no)
for b.Controls[0].Op == OpAMD64SETL {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64LT, cmp)
return true
}
// match: (If (SETLE cmp) yes no)
// result: (LE cmp yes no)
for b.Controls[0].Op == OpAMD64SETLE {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64LE, cmp)
return true
}
// match: (If (SETG cmp) yes no)
// result: (GT cmp yes no)
for b.Controls[0].Op == OpAMD64SETG {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64GT, cmp)
return true
}
// match: (If (SETGE cmp) yes no)
// result: (GE cmp yes no)
for b.Controls[0].Op == OpAMD64SETGE {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64GE, cmp)
return true
}
// match: (If (SETEQ cmp) yes no)
// result: (EQ cmp yes no)
for b.Controls[0].Op == OpAMD64SETEQ {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64EQ, cmp)
return true
}
// match: (If (SETNE cmp) yes no)
// result: (NE cmp yes no)
for b.Controls[0].Op == OpAMD64SETNE {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64NE, cmp)
return true
}
// match: (If (SETB cmp) yes no)
// result: (ULT cmp yes no)
for b.Controls[0].Op == OpAMD64SETB {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64ULT, cmp)
return true
}
// match: (If (SETBE cmp) yes no)
// result: (ULE cmp yes no)
for b.Controls[0].Op == OpAMD64SETBE {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64ULE, cmp)
return true
}
// match: (If (SETA cmp) yes no)
// result: (UGT cmp yes no)
for b.Controls[0].Op == OpAMD64SETA {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGT, cmp)
return true
}
// match: (If (SETAE cmp) yes no)
// result: (UGE cmp yes no)
for b.Controls[0].Op == OpAMD64SETAE {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGE, cmp)
return true
}
// match: (If (SETO cmp) yes no)
// result: (OS cmp yes no)
for b.Controls[0].Op == OpAMD64SETO {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64OS, cmp)
return true
}
// match: (If (SETGF cmp) yes no)
// result: (UGT cmp yes no)
for b.Controls[0].Op == OpAMD64SETGF {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGT, cmp)
return true
}
// match: (If (SETGEF cmp) yes no)
// result: (UGE cmp yes no)
for b.Controls[0].Op == OpAMD64SETGEF {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGE, cmp)
return true
}
// match: (If (SETEQF cmp) yes no)
// result: (EQF cmp yes no)
for b.Controls[0].Op == OpAMD64SETEQF {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64EQF, cmp)
return true
}
// match: (If (SETNEF cmp) yes no)
// result: (NEF cmp yes no)
for b.Controls[0].Op == OpAMD64SETNEF {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64NEF, cmp)
return true
}
// match: (If cond yes no)
// result: (NE (TESTB cond cond) yes no)
for {
cond := b.Controls[0]
v0 := b.NewValue0(cond.Pos, OpAMD64TESTB, types.TypeFlags)
v0.AddArg2(cond, cond)
b.resetWithControl(BlockAMD64NE, v0)
return true
}
case BlockAMD64LE:
// match: (LE (InvertFlags cmp) yes no)
// result: (GE cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64GE, cmp)
return true
}
// match: (LE (FlagEQ) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
return true
}
// match: (LE (FlagLT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (LE (FlagLT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
return true
}
// match: (LE (FlagGT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (LE (FlagGT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
case BlockAMD64LT:
// match: (LT (InvertFlags cmp) yes no)
// result: (GT cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64GT, cmp)
return true
}
// match: (LT (FlagEQ) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (LT (FlagLT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (LT (FlagLT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
return true
}
// match: (LT (FlagGT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (LT (FlagGT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
case BlockAMD64NE:
// match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no)
// result: (LT cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETL {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETL || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64LT, cmp)
return true
}
// match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no)
// result: (LE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETLE {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETLE || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64LE, cmp)
return true
}
// match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no)
// result: (GT cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETG {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETG || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64GT, cmp)
return true
}
// match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no)
// result: (GE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETGE {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETGE || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64GE, cmp)
return true
}
// match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no)
// result: (EQ cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETEQ {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETEQ || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64EQ, cmp)
return true
}
// match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no)
// result: (NE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETNE {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETNE || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64NE, cmp)
return true
}
// match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no)
// result: (ULT cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETB {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETB || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64ULT, cmp)
return true
}
// match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no)
// result: (ULE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETBE {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETBE || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64ULE, cmp)
return true
}
// match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no)
// result: (UGT cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETA {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETA || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64UGT, cmp)
return true
}
// match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no)
// result: (UGE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETAE {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETAE || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64UGE, cmp)
return true
}
// match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no)
// result: (OS cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETO {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETO || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64OS, cmp)
return true
}
// match: (NE (TESTL (SHLL (MOVLconst [1]) x) y))
// result: (ULT (BTL x y))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64SHLL {
continue
}
x := v_0_0.Args[1]
v_0_0_0 := v_0_0.Args[0]
if v_0_0_0.Op != OpAMD64MOVLconst || auxIntToInt32(v_0_0_0.AuxInt) != 1 {
continue
}
y := v_0_1
v0 := b.NewValue0(v_0.Pos, OpAMD64BTL, types.TypeFlags)
v0.AddArg2(x, y)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y))
// result: (ULT (BTQ x y))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64SHLQ {
continue
}
x := v_0_0.Args[1]
v_0_0_0 := v_0_0.Args[0]
if v_0_0_0.Op != OpAMD64MOVQconst || auxIntToInt64(v_0_0_0.AuxInt) != 1 {
continue
}
y := v_0_1
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQ, types.TypeFlags)
v0.AddArg2(x, y)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTLconst [c] x))
// cond: isUint32PowerOfTwo(int64(c))
// result: (ULT (BTLconst [int8(log32(c))] x))
for b.Controls[0].Op == OpAMD64TESTLconst {
v_0 := b.Controls[0]
c := auxIntToInt32(v_0.AuxInt)
x := v_0.Args[0]
if !(isUint32PowerOfTwo(int64(c))) {
break
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log32(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
// match: (NE (TESTQconst [c] x))
// cond: isUint64PowerOfTwo(int64(c))
// result: (ULT (BTQconst [int8(log32(c))] x))
for b.Controls[0].Op == OpAMD64TESTQconst {
v_0 := b.Controls[0]
c := auxIntToInt32(v_0.AuxInt)
x := v_0.Args[0]
if !(isUint64PowerOfTwo(int64(c))) {
break
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log32(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
// match: (NE (TESTQ (MOVQconst [c]) x))
// cond: isUint64PowerOfTwo(c)
// result: (ULT (BTQconst [int8(log64(c))] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
if v_0_0.Op != OpAMD64MOVQconst {
continue
}
c := auxIntToInt64(v_0_0.AuxInt)
x := v_0_1
if !(isUint64PowerOfTwo(c)) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(int8(log64(c)))
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
// cond: z1==z2
// result: (ULT (BTQconst [63] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHLQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 63 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(63)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
// cond: z1==z2
// result: (ULT (BTQconst [31] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHLLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHRQconst || auxIntToInt8(z1_0.AuxInt) != 31 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(31)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
// cond: z1==z2
// result: (ULT (BTQconst [0] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHLQconst || auxIntToInt8(z1_0.AuxInt) != 63 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(0)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
// cond: z1==z2
// result: (ULT (BTLconst [0] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
z1_0 := z1.Args[0]
if z1_0.Op != OpAMD64SHLLconst || auxIntToInt8(z1_0.AuxInt) != 31 {
continue
}
x := z1_0.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(0)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTQ z1:(SHRQconst [63] x) z2))
// cond: z1==z2
// result: (ULT (BTQconst [63] x))
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRQconst || auxIntToInt8(z1.AuxInt) != 63 {
continue
}
x := z1.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTQconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(63)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTL z1:(SHRLconst [31] x) z2))
// cond: z1==z2
// result: (ULT (BTLconst [31] x))
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
v_0_1 := v_0.Args[1]
for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
z1 := v_0_0
if z1.Op != OpAMD64SHRLconst || auxIntToInt8(z1.AuxInt) != 31 {
continue
}
x := z1.Args[0]
z2 := v_0_1
if !(z1 == z2) {
continue
}
v0 := b.NewValue0(v_0.Pos, OpAMD64BTLconst, types.TypeFlags)
v0.AuxInt = int8ToAuxInt(31)
v0.AddArg(x)
b.resetWithControl(BlockAMD64ULT, v0)
return true
}
break
}
// match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no)
// result: (UGT cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETGF {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETGF || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64UGT, cmp)
return true
}
// match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no)
// result: (UGE cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETGEF {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETGEF || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64UGE, cmp)
return true
}
// match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no)
// result: (EQF cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETEQF {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETEQF || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64EQF, cmp)
return true
}
// match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no)
// result: (NEF cmp yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
_ = v_0.Args[1]
v_0_0 := v_0.Args[0]
if v_0_0.Op != OpAMD64SETNEF {
break
}
cmp := v_0_0.Args[0]
v_0_1 := v_0.Args[1]
if v_0_1.Op != OpAMD64SETNEF || cmp != v_0_1.Args[0] {
break
}
b.resetWithControl(BlockAMD64NEF, cmp)
return true
}
// match: (NE (InvertFlags cmp) yes no)
// result: (NE cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64NE, cmp)
return true
}
// match: (NE (FlagEQ) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (NE (FlagLT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (NE (FlagLT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
return true
}
// match: (NE (FlagGT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (NE (FlagGT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
return true
}
case BlockAMD64UGE:
// match: (UGE (TESTQ x x) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
return true
}
// match: (UGE (TESTL x x) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
return true
}
// match: (UGE (TESTW x x) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64TESTW {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
return true
}
// match: (UGE (TESTB x x) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
return true
}
// match: (UGE (InvertFlags cmp) yes no)
// result: (ULE cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64ULE, cmp)
return true
}
// match: (UGE (FlagEQ) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
return true
}
// match: (UGE (FlagLT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (UGE (FlagLT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
return true
}
// match: (UGE (FlagGT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (UGE (FlagGT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
return true
}
case BlockAMD64UGT:
// match: (UGT (InvertFlags cmp) yes no)
// result: (ULT cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64ULT, cmp)
return true
}
// match: (UGT (FlagEQ) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (UGT (FlagLT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (UGT (FlagLT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
return true
}
// match: (UGT (FlagGT_ULT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (UGT (FlagGT_UGT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
return true
}
case BlockAMD64ULE:
// match: (ULE (InvertFlags cmp) yes no)
// result: (UGE cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGE, cmp)
return true
}
// match: (ULE (FlagEQ) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
return true
}
// match: (ULE (FlagLT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (ULE (FlagLT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULE (FlagGT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (ULE (FlagGT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
case BlockAMD64ULT:
// match: (ULT (TESTQ x x) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64TESTQ {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (TESTL x x) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64TESTL {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (TESTW x x) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64TESTW {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (TESTB x x) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64TESTB {
v_0 := b.Controls[0]
x := v_0.Args[1]
if x != v_0.Args[0] {
break
}
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (InvertFlags cmp) yes no)
// result: (UGT cmp yes no)
for b.Controls[0].Op == OpAMD64InvertFlags {
v_0 := b.Controls[0]
cmp := v_0.Args[0]
b.resetWithControl(BlockAMD64UGT, cmp)
return true
}
// match: (ULT (FlagEQ) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagEQ {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (FlagLT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagLT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (ULT (FlagLT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagLT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
// match: (ULT (FlagGT_ULT) yes no)
// result: (First yes no)
for b.Controls[0].Op == OpAMD64FlagGT_ULT {
b.Reset(BlockFirst)
return true
}
// match: (ULT (FlagGT_UGT) yes no)
// result: (First no yes)
for b.Controls[0].Op == OpAMD64FlagGT_UGT {
b.Reset(BlockFirst)
b.swapSuccessors()
return true
}
}
return false
}