static void __init axs103_early_init()

in plat-axs10x/axs10x.c [301:350]

• 28 lines of code
• 3 McCabe index (conditional complexity)

static void __init axs103_early_init(void)
{
#ifdef CONFIG_ARC_MCIP
	/*
	 * AXS103 configurations for SMP/QUAD configurations share device tree
	 * which defaults to 100 MHz. However recent failures of Quad config
	 * revealed P&R timing violations so clamp it down to safe 50 MHz
	 * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
	 * of fudging the freq in DT
	 */
#define AXS103_QUAD_CORE_CPU_FREQ_HZ	50000000

	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
	if (num_cores > 2) {
		u32 freq;
		int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
		const struct fdt_property *prop;

		prop = fdt_get_property(initial_boot_params, off,
					"assigned-clock-rates", NULL);
		freq = be32_to_cpu(*(u32 *)(prop->data));

		/* Patching .dtb in-place with new core clock value */
		if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
			freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
			fdt_setprop_inplace(initial_boot_params, off,
					    "assigned-clock-rates", &freq, sizeof(freq));
		}
	}
#endif

	/* Memory maps already config in pre-bootloader */

	/* set GPIO mux to UART */
	iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);

	iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
		  (void __iomem *) CREG_CPU_TUN_IO_CTRL);

	/* Set up the AXS_MB interrupt system.*/
	iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
					 + (AXC003_MST_HS38 << 2)));

	/* connect ICTL - Main Board with GPIO line */
	iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);

	axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");

	axs10x_early_init();
}