mach-omap2/sram242x.S [47:96]:
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	ldr	r10, [r11]		@ get current val
	cmp	r12, #0x1		@ cs1 base (2422 es2.05/1)
	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
	mvn	r9, #0x4		@ mask to get clear bit2
	and	r10, r10, r9		@ clear bit2 for lock mode.
	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
	orr	r10, r10, #0x2		@ 90 degree phase for all below 133MHz
	str	r10, [r11]		@ commit to DLLA_CTRL
	bl	i_dll_wait		@ wait for dll to lock

	/* get dll value */
	add	r11, r11, #0x4		@ get addr of status reg
	ldr	r10, [r11]		@ get locked value

	/* voltage shift up */
	mov r9, #0x0			@ shift back to L0-voltage
	bl voltage_shift		@ go raise voltage

	/* frequency shift up */
	mov	r3, #0x2		@ value for 2x operation
	str	r3, [r2]		@ go to L0-freq operation

	/* reset entry mode for dllctrl */
	sub	r11, r11, #0x4		@ move from status to ctrl
	cmp	r12, #0x1		@ normalize if cs1 based
	subeq	r11, r11, #0x8		@ possibly back to DLLA
	cmp	r8, #0x1		@ if forced unlock exit
	orreq	r1, r1, #0x4		@ make sure exit with unlocked value
	str	r1, [r11]		@ restore DLLA_CTRL high value
	add	r11, r11, #0x8		@ move to DLLB_CTRL addr
	str	r1, [r11]		@ set value DLLB_CTRL
	bl	i_dll_wait		@ wait for possible lock

	/* set up for return, DDR should be good */
	str r10, [r0]			@ write dll_status and return counter
	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return

	/* ensure the DLL has relocked */
i_dll_wait:
	mov	r4, #0x800		@ delay DLL relock, min 0x400 L3 clocks
i_dll_delay:
	subs	r4, r4, #0x1
	bne	i_dll_delay
	ret	lr

	/*
	 * shift up or down voltage, use R9 as input to tell level.
	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
	 */
voltage_shift:
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mach-omap2/sram243x.S [47:96]:
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	ldr	r10, [r11]		@ get current val
	cmp	r12, #0x1		@ cs1 base (2422 es2.05/1)
	addeq	r11, r11, #0x8		@ if cs1 base, move to DLLB
	mvn	r9, #0x4		@ mask to get clear bit2
	and	r10, r10, r9		@ clear bit2 for lock mode.
	orr	r10, r10, #0x8		@ make sure DLL on (es2 bit pos)
	orr	r10, r10, #0x2		@ 90 degree phase for all below 133MHz
	str	r10, [r11]		@ commit to DLLA_CTRL
	bl	i_dll_wait		@ wait for dll to lock

	/* get dll value */
	add	r11, r11, #0x4		@ get addr of status reg
	ldr	r10, [r11]		@ get locked value

	/* voltage shift up */
	mov r9, #0x0			@ shift back to L0-voltage
	bl voltage_shift		@ go raise voltage

	/* frequency shift up */
	mov	r3, #0x2		@ value for 2x operation
	str	r3, [r2]		@ go to L0-freq operation

	/* reset entry mode for dllctrl */
	sub	r11, r11, #0x4		@ move from status to ctrl
	cmp	r12, #0x1		@ normalize if cs1 based
	subeq	r11, r11, #0x8		@ possibly back to DLLA
	cmp	r8, #0x1		@ if forced unlock exit
	orreq	r1, r1, #0x4		@ make sure exit with unlocked value
	str	r1, [r11]		@ restore DLLA_CTRL high value
	add	r11, r11, #0x8		@ move to DLLB_CTRL addr
	str	r1, [r11]		@ set value DLLB_CTRL
	bl	i_dll_wait		@ wait for possible lock

	/* set up for return, DDR should be good */
	str r10, [r0]			@ write dll_status and return counter
	ldmfd	sp!, {r0 - r12, pc}	@ restore regs and return

	/* ensure the DLL has relocked */
i_dll_wait:
	mov	r4, #0x800		@ delay DLL relock, min 0x400 L3 clocks
i_dll_delay:
	subs	r4, r4, #0x1
	bne	i_dll_delay
	ret	lr

	/*
	 * shift up or down voltage, use R9 as input to tell level.
	 * wait for it to finish, use 32k sync counter, 1tick=31uS.
	 */
voltage_shift:
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