in mm/tlb.c [168:197]
void flush_tlb_one(unsigned long addr)
{
addr &= TLB_ENTRY_SIZE_MASK;
#ifdef CONFIG_CPU_HAS_TLBI
sync_is();
asm volatile(
"tlbi.vaas %0 \n"
"sync.i \n"
:
: "r" (addr)
: "memory");
#else
{
int oldpid, idx;
unsigned long flags;
local_irq_save(flags);
oldpid = read_mmu_entryhi() & ASID_MASK;
write_mmu_entryhi(addr | oldpid);
tlb_probe();
idx = read_mmu_index();
if (idx >= 0)
tlb_invalid_indexed();
restore_asid_inv_utlb(oldpid, oldpid);
local_irq_restore(flags);
}
#endif
}