void flush_tlb_kernel_range()

in mm/tlb.c [95:133]


void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	start &= TLB_ENTRY_SIZE_MASK;
	end   += TLB_ENTRY_SIZE - 1;
	end   &= TLB_ENTRY_SIZE_MASK;

#ifdef CONFIG_CPU_HAS_TLBI
	sync_is();
	while (start < end) {
		asm volatile(
			"tlbi.vaas %0	\n"
			:
			: "r" (start)
			: "memory");

		start += 2*PAGE_SIZE;
	}
	asm volatile("sync.i\n");
#else
	{
	unsigned long flags, oldpid;

	local_irq_save(flags);
	oldpid = read_mmu_entryhi() & ASID_MASK;
	while (start < end) {
		int idx;

		write_mmu_entryhi(start | oldpid);
		start += 2*PAGE_SIZE;
		tlb_probe();
		idx = read_mmu_index();
		if (idx >= 0)
			tlb_invalid_indexed();
	}
	restore_asid_inv_utlb(oldpid, oldpid);
	local_irq_restore(flags);
	}
#endif
}