in pata_octeon_cf.c [802:976]
static int octeon_cf_probe(struct platform_device *pdev)
{
struct resource *res_cs0, *res_cs1;
bool is_16bit;
const __be32 *cs_num;
struct property *reg_prop;
int n_addr, n_size, reg_len;
struct device_node *node;
void __iomem *cs0;
void __iomem *cs1 = NULL;
struct ata_host *host;
struct ata_port *ap;
int irq = 0;
irq_handler_t irq_handler = NULL;
void __iomem *base;
struct octeon_cf_port *cf_port;
int rv = -ENOMEM;
u32 bus_width;
node = pdev->dev.of_node;
if (node == NULL)
return -EINVAL;
cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
if (!cf_port)
return -ENOMEM;
cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)
is_16bit = (bus_width == 16);
else
is_16bit = false;
n_addr = of_n_addr_cells(node);
n_size = of_n_size_cells(node);
reg_prop = of_find_property(node, "reg", ®_len);
if (!reg_prop || reg_len < sizeof(__be32))
return -EINVAL;
cs_num = reg_prop->value;
cf_port->cs0 = be32_to_cpup(cs_num);
if (cf_port->is_true_ide) {
struct device_node *dma_node;
dma_node = of_parse_phandle(node,
"cavium,dma-engine-handle", 0);
if (dma_node) {
struct platform_device *dma_dev;
dma_dev = of_find_device_by_node(dma_node);
if (dma_dev) {
struct resource *res_dma;
int i;
res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
if (!res_dma) {
of_node_put(dma_node);
return -EINVAL;
}
cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
resource_size(res_dma));
if (!cf_port->dma_base) {
of_node_put(dma_node);
return -EINVAL;
}
i = platform_get_irq(dma_dev, 0);
if (i > 0) {
irq = i;
irq_handler = octeon_cf_interrupt;
}
}
of_node_put(dma_node);
}
res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res_cs1)
return -EINVAL;
cs1 = devm_ioremap(&pdev->dev, res_cs1->start,
resource_size(res_cs1));
if (!cs1)
return rv;
if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
return -EINVAL;
cs_num += n_addr + n_size;
cf_port->cs1 = be32_to_cpup(cs_num);
}
res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res_cs0)
return -EINVAL;
cs0 = devm_ioremap(&pdev->dev, res_cs0->start,
resource_size(res_cs0));
if (!cs0)
return rv;
/* allocate host */
host = ata_host_alloc(&pdev->dev, 1);
if (!host)
return rv;
ap = host->ports[0];
ap->private_data = cf_port;
pdev->dev.platform_data = cf_port;
cf_port->ap = ap;
ap->ops = &octeon_cf_ops;
ap->pio_mask = ATA_PIO6;
ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
if (!is_16bit) {
base = cs0 + 0x800;
ap->ioaddr.cmd_addr = base;
ata_sff_std_ports(&ap->ioaddr);
ap->ioaddr.altstatus_addr = base + 0xe;
ap->ioaddr.ctl_addr = base + 0xe;
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
} else if (cf_port->is_true_ide) {
base = cs0;
ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1);
ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1;
ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1;
ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1;
ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1;
ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1;
ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1;
ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1;
ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0;
/* True IDE mode needs a timer to poll for not-busy. */
hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
cf_port->delayed_finish.function = octeon_cf_delayed_finish;
} else {
/* 16 bit but not True IDE */
base = cs0 + 0x800;
octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
octeon_cf_ops.softreset = octeon_cf_softreset16;
octeon_cf_ops.sff_check_status = octeon_cf_check_status16;
octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16;
octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16;
octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16;
ap->ioaddr.data_addr = base + ATA_REG_DATA;
ap->ioaddr.nsect_addr = base + ATA_REG_NSECT;
ap->ioaddr.lbal_addr = base + ATA_REG_LBAL;
ap->ioaddr.ctl_addr = base + 0xe;
ap->ioaddr.altstatus_addr = base + 0xe;
}
cf_port->c0 = ap->ioaddr.ctl_addr;
rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
if (rv)
return rv;
ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
is_16bit ? 16 : 8,
cf_port->is_true_ide ? ", True IDE" : "");
return ata_host_activate(host, irq, irq_handler,
IRQF_SHARED, &octeon_cf_sht);
}