static int ahci_qoriq_phy_init()

in ahci_qoriq.c [166:256]

• 84 lines of code
• 31 McCabe index (conditional complexity)

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_ARMV8_CH2,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1028A:
	case AHCI_LS1088A:
	case AHCI_LX2160A:
		if (!(qpriv->ecc_addr || ecc_initialized))
			return -EINVAL;
		else if (qpriv->ecc_addr && !ecc_initialized)
			writel(readl(qpriv->ecc_addr) |
			       ECC_DIS_LS1088A,
			       qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2088A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	ecc_initialized = true;
	return 0;
}