static u32 sysc_quirk_dispc()

in ti-sysc.c [1773:1852]


static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
			    bool disable)
{
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
	int manager_count;
	bool framedonetv_irq = true;
	u32 val, irq_mask = 0;

	switch (sysc_soc->soc) {
	case SOC_2420 ... SOC_3630:
		manager_count = 2;
		framedonetv_irq = false;
		break;
	case SOC_4430 ... SOC_4470:
		manager_count = 3;
		break;
	case SOC_5430:
	case SOC_DRA7:
		manager_count = 4;
		break;
	case SOC_AM4:
		manager_count = 1;
		framedonetv_irq = false;
		break;
	case SOC_UNKNOWN:
	default:
		return 0;
	}

	/* Remap the whole module range to be able to reset dispc outputs */
	devm_iounmap(ddata->dev, ddata->module_va);
	ddata->module_va = devm_ioremap(ddata->dev,
					ddata->module_pa,
					ddata->module_size);
	if (!ddata->module_va)
		return -EIO;

	/* DISP_CONTROL */
	val = sysc_read(ddata, dispc_offset + 0x40);
	lcd_en = val & lcd_en_mask;
	digit_en = val & digit_en_mask;
	if (lcd_en)
		irq_mask |= BIT(0);			/* FRAMEDONE */
	if (digit_en) {
		if (framedonetv_irq)
			irq_mask |= BIT(24);		/* FRAMEDONETV */
		else
			irq_mask |= BIT(2) | BIT(3);	/* EVSYNC bits */
	}
	if (disable & (lcd_en | digit_en))
		sysc_write(ddata, dispc_offset + 0x40,
			   val & ~(lcd_en_mask | digit_en_mask));

	if (manager_count <= 2)
		return irq_mask;

	/* DISPC_CONTROL2 */
	val = sysc_read(ddata, dispc_offset + 0x238);
	lcd2_en = val & lcd_en_mask;
	if (lcd2_en)
		irq_mask |= BIT(22);			/* FRAMEDONE2 */
	if (disable && lcd2_en)
		sysc_write(ddata, dispc_offset + 0x238,
			   val & ~lcd_en_mask);

	if (manager_count <= 3)
		return irq_mask;

	/* DISPC_CONTROL3 */
	val = sysc_read(ddata, dispc_offset + 0x848);
	lcd3_en = val & lcd_en_mask;
	if (lcd3_en)
		irq_mask |= BIT(30);			/* FRAMEDONE3 */
	if (disable && lcd3_en)
		sysc_write(ddata, dispc_offset + 0x848,
			   val & ~lcd_en_mask);

	return irq_mask;
}