in sunxi-ng/ccu-sun4i-a10.c [1039:1210]
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
clk_parent_pll_audio,
1, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
clk_parent_pll_audio,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
&pll_video0_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
&pll_video1_clk.common.hw,
1, 2, CLK_SET_RATE_PARENT);
static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
.hws = {
[CLK_HOSC] = &hosc_clk.common.hw,
[CLK_PLL_CORE] = &pll_core_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
[CLK_PLL_AUDIO] = &pll_audio_clk.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
[CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
[CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
[CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
[CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
[CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
[CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
[CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
[CLK_PLL_PERIPH] = &pll_periph_clk.hw,
[CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
[CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
[CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
[CLK_CPU] = &cpu_clk.common.hw,
[CLK_AXI] = &axi_clk.common.hw,
[CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
[CLK_AHB] = &ahb_sun4i_clk.common.hw,
[CLK_APB0] = &apb0_clk.common.hw,
[CLK_APB1] = &apb1_clk.common.hw,
[CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
[CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
[CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
[CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
[CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
[CLK_AHB_SS] = &ahb_ss_clk.common.hw,
[CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
[CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
[CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
[CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
[CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
[CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
[CLK_AHB_MS] = &ahb_ms_clk.common.hw,
[CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
[CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
[CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
[CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
[CLK_AHB_TS] = &ahb_ts_clk.common.hw,
[CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
[CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
[CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
[CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
[CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
[CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
[CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
[CLK_AHB_VE] = &ahb_ve_clk.common.hw,
[CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
[CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
[CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
[CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
[CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
[CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
[CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
[CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
[CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
[CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
[CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
[CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
[CLK_AHB_MP] = &ahb_mp_clk.common.hw,
[CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
[CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
[CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
[CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
[CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
[CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
[CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
[CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
[CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
[CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
[CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
[CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
[CLK_APB1_CAN] = &apb1_can_clk.common.hw,
[CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
[CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
[CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
[CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
[CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
[CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
[CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
[CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
[CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
[CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
[CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_MS] = &ms_clk.common.hw,
[CLK_MMC0] = &mmc0_clk.common.hw,
[CLK_MMC1] = &mmc1_clk.common.hw,
[CLK_MMC2] = &mmc2_clk.common.hw,
[CLK_MMC3] = &mmc3_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_SS] = &ss_clk.common.hw,
[CLK_SPI0] = &spi0_clk.common.hw,
[CLK_SPI1] = &spi1_clk.common.hw,
[CLK_SPI2] = &spi2_clk.common.hw,
[CLK_PATA] = &pata_clk.common.hw,
[CLK_IR0] = &ir0_sun4i_clk.common.hw,
[CLK_IR1] = &ir1_sun4i_clk.common.hw,
[CLK_I2S0] = &i2s0_clk.common.hw,
[CLK_AC97] = &ac97_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_KEYPAD] = &keypad_clk.common.hw,
[CLK_SATA] = &sata_clk.common.hw,
[CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
[CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
[CLK_USB_PHY] = &usb_phy_clk.common.hw,
/* CLK_GPS is unimplemented */
[CLK_SPI3] = &spi3_clk.common.hw,
[CLK_DRAM_VE] = &dram_ve_clk.common.hw,
[CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
[CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
[CLK_DRAM_TS] = &dram_ts_clk.common.hw,
[CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
[CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
[CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
[CLK_DRAM_OUT] = &dram_out_clk.common.hw,
[CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
[CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
[CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
[CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
[CLK_DRAM_MP] = &dram_mp_clk.common.hw,
[CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
[CLK_DE_BE0] = &de_be0_clk.common.hw,
[CLK_DE_BE1] = &de_be1_clk.common.hw,
[CLK_DE_FE0] = &de_fe0_clk.common.hw,
[CLK_DE_FE1] = &de_fe1_clk.common.hw,
[CLK_DE_MP] = &de_mp_clk.common.hw,
[CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
[CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
[CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
[CLK_TVD] = &tvd_sun4i_clk.common.hw,
[CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
[CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
[CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
[CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
[CLK_CSI0] = &csi0_clk.common.hw,
[CLK_CSI1] = &csi1_clk.common.hw,
[CLK_VE] = &ve_clk.common.hw,
[CLK_CODEC] = &codec_clk.common.hw,
[CLK_AVS] = &avs_clk.common.hw,
[CLK_ACE] = &ace_clk.common.hw,
[CLK_HDMI] = &hdmi_clk.common.hw,
[CLK_GPU] = &gpu_sun7i_clk.common.hw,
[CLK_MBUS] = &mbus_sun4i_clk.common.hw,
},
.num = CLK_NUMBER_SUN4I,
};