in clk-stm32f4.c [1684:1900]
static void __init stm32f4_rcc_init(struct device_node *np)
{
const char *hse_clk, *i2s_in_clk;
int n;
const struct of_device_id *match;
const struct stm32f4_clk_data *data;
unsigned long pllm;
struct clk_hw *pll_src_hw;
base = of_iomap(np, 0);
if (!base) {
pr_err("%pOFn: unable to map resource\n", np);
return;
}
pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(pdrm)) {
pdrm = NULL;
pr_warn("%s: Unable to get syscfg\n", __func__);
}
match = of_match_node(stm32f4_of_match, np);
if (WARN_ON(!match))
return;
data = match->data;
stm32fx_end_primary_clk = data->end_primary;
clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
sizeof(*clks), GFP_KERNEL);
if (!clks)
goto fail;
stm32f4_gate_map = data->gates_map;
hse_clk = of_clk_get_parent_name(np, 0);
dsi_parent[0] = hse_clk;
pllsrc_parent[1] = hse_clk;
i2s_in_clk = of_clk_get_parent_name(np, 1);
i2s_parents[1] = i2s_in_clk;
sai_parents[2] = i2s_in_clk;
if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
base + STM32F4_RCC_APB2ENR, 29,
CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
dsi_parent[0] = pll_src;
sai_parents[3] = pll_src;
}
clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
NULL, 0, 16000000, 160000);
pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
ARRAY_SIZE(pllsrc_parent), 0,
base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
&stm32f4_clk_lock);
pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
0, 1, pllm);
stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
&stm32f4_clk_lock);
clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
&data->pll_data[1], &stm32f4_clk_lock);
clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
&data->pll_data[2], &stm32f4_clk_lock);
for (n = 0; n < MAX_POST_DIV; n++) {
const struct stm32f4_pll_post_div_data *post_div;
struct clk_hw *hw;
post_div = &post_div_data[n];
hw = clk_register_pll_div(post_div->name,
post_div->parent,
post_div->flag,
base + post_div->offset,
post_div->shift,
post_div->width,
post_div->flag_div,
post_div->div_table,
clks[post_div->pll_idx],
&stm32f4_clk_lock);
if (post_div->idx != NO_IDX)
clks[post_div->idx] = hw;
}
sys_parents[1] = hse_clk;
clks[CLK_SYSCLK] = clk_hw_register_mux_table(
NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
clk_register_divider_table(NULL, "ahb_div", "sys",
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
clk_register_divider_table(NULL, "apb1_div", "ahb_div",
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
10, 3, 0, apb_div_table, &stm32f4_clk_lock);
clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
CLK_SET_RATE_PARENT, 12);
clk_register_divider_table(NULL, "apb2_div", "ahb_div",
CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
13, 3, 0, apb_div_table, &stm32f4_clk_lock);
clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
CLK_SET_RATE_PARENT, 15);
clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
0, 1, 8);
clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
0, 1, 1);
for (n = 0; n < data->gates_num; n++) {
const struct stm32f4_gate_data *gd;
unsigned int secondary;
int idx;
gd = &data->gates_data[n];
secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
gd->bit_idx;
idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
if (idx < 0)
goto fail;
clks[idx] = clk_hw_register_gate(
NULL, gd->name, gd->parent_name, gd->flags,
base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[idx])) {
pr_err("%pOF: Unable to register leaf clock %s\n",
np, gd->name);
goto fail;
}
}
clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[CLK_LSI])) {
pr_err("Unable to register lsi clock\n");
goto fail;
}
clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[CLK_LSE])) {
pr_err("Unable to register lse clock\n");
goto fail;
}
clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
0, base + STM32F4_RCC_CFGR, 16, 5, 0,
&stm32f4_clk_lock);
if (IS_ERR(clks[CLK_HSE_RTC])) {
pr_err("Unable to register hse-rtc clock\n");
goto fail;
}
clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[CLK_RTC])) {
pr_err("Unable to register rtc clock\n");
goto fail;
}
for (n = 0; n < data->aux_clk_num; n++) {
const struct stm32_aux_clk *aux_clk;
struct clk_hw *hw;
aux_clk = &data->aux_clk[n];
hw = stm32_register_aux_clk(aux_clk->name,
aux_clk->parent_names, aux_clk->num_parents,
aux_clk->offset_mux, aux_clk->shift,
aux_clk->mask, aux_clk->offset_gate,
aux_clk->bit_idx, aux_clk->flags,
&stm32f4_clk_lock);
if (IS_ERR(hw)) {
pr_warn("Unable to register %s clk\n", aux_clk->name);
continue;
}
if (aux_clk->idx != NO_IDX)
clks[aux_clk->idx] = hw;
}
if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1, 488);
clks[CLK_PLL_SRC] = pll_src_hw;
}
of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
return;
fail:
kfree(clks);
iounmap(base);
}