in actions/owl-s900.c [240:592]
static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
0);
static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
OWL_MUX_HW(CMU_CSICLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
0);
static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
OWL_MUX_HW(CMU_CSICLK, 20, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
0);
static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
OWL_MUX_HW(CMU_DECLK, 12, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
0);
static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
OWL_MUX_HW(CMU_BUSCLK, 10, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
CLK_IGNORE_UNUSED);
static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
OWL_MUX_HW(CMU_EDPCLK, 19, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
0);
static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
0);
static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
0);
static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
0);
static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
0);
static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_HDECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
0);
static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
0);
static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
1, 5, 0);
static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
1, 5, 0);
static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
0);
static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
0);
static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
OWL_MUX_HW(CMU_IMXCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
0);
static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
OWL_MUX_HW(CMU_LCDCLK, 12, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
0);
static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
CLK_SET_RATE_PARENT);
static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
CLK_SET_RATE_PARENT);
static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
0);
static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
0);
/*
* pwm2 may be for backlight, do not gate it
* even it is "unused", because it may be
* enabled at boot stage, and in kernel, driver
* has no effective method to know the real status,
* so, the best way is keeping it as what it was.
*/
static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
0);
static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
0);
static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
0);
static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
0);
static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD1CLK, 9, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
0);
static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD2CLK, 9, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
0);
static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD3CLK, 9, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
0);
static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
0);
static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
"hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
0);
static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
"hosc",
OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
0);
static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART1CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
0);
static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_VDECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
0);
static struct owl_clk_common *s900_clks[] = {
&core_pll_clk.common,
&dev_pll_clk.common,
&ddr_pll_clk.common,
&nand_pll_clk.common,
&display_pll_clk.common,
&assist_pll_clk.common,
&audio_pll_clk.common,
&edp_pll_clk.common,
&cpu_clk.common,
&dev_clk.common,
&noc_clk_mux.common,
&noc_clk_div.common,
&ahb_clk.common,
&apb_clk.common,
&usb3_mac_clk.common,
&rmii_ref_clk.common,
&noc_clk.common,
&de_clk1.common,
&de_clk2.common,
&de_clk3.common,
&gpio_clk.common,
&gpu_clk.common,
&dmac_clk.common,
&timer_clk.common,
&dsi_clk.common,
&ddr0_clk.common,
&ddr1_clk.common,
&usb3_480mpll0_clk.common,
&usb3_480mphy0_clk.common,
&usb3_5gphy_clk.common,
&usb3_cce_clk.common,
&edp24M_clk.common,
&edp_link_clk.common,
&usbh0_pllen_clk.common,
&usbh0_phy_clk.common,
&usbh0_cce_clk.common,
&usbh1_pllen_clk.common,
&usbh1_phy_clk.common,
&usbh1_cce_clk.common,
&i2c0_clk.common,
&i2c1_clk.common,
&i2c2_clk.common,
&i2c3_clk.common,
&i2c4_clk.common,
&i2c5_clk.common,
&spi0_clk.common,
&spi1_clk.common,
&spi2_clk.common,
&spi3_clk.common,
&bisp_clk.common,
&csi0_clk.common,
&csi1_clk.common,
&de_clk.common,
&dmm_clk.common,
&edp_clk.common,
ð_mac_clk.common,
&gpu_core_clk.common,
&gpu_mem_clk.common,
&gpu_sys_clk.common,
&hde_clk.common,
&hdmia_clk.common,
&i2srx_clk.common,
&i2stx_clk.common,
&imx_clk.common,
&lcd_clk.common,
&nand0_clk.common,
&nand1_clk.common,
&pwm0_clk.common,
&pwm1_clk.common,
&pwm2_clk.common,
&pwm3_clk.common,
&pwm4_clk.common,
&pwm5_clk.common,
&sd0_clk.common,
&sd1_clk.common,
&sd2_clk.common,
&sd3_clk.common,
&sensor_clk.common,
&speed_sensor_clk.common,
&thermal_sensor_clk.common,
&uart0_clk.common,
&uart1_clk.common,
&uart2_clk.common,
&uart3_clk.common,
&uart4_clk.common,
&uart5_clk.common,
&uart6_clk.common,
&vce_clk.common,
&vde_clk.common,
};