in intel-qep.c [275:322]
static int intel_qep_spike_filter_ns_write(struct counter_device *counter,
struct counter_count *count,
u64 length)
{
struct intel_qep *qep = counter_priv(counter);
u32 reg;
bool enable;
int ret = 0;
/*
* Spike filter length is (MAX_COUNT + 2) clock periods.
* Disable filter when userspace writes 0, enable for valid
* nanoseconds values and error out otherwise.
*/
do_div(length, INTEL_QEP_CLK_PERIOD_NS);
if (length == 0) {
enable = false;
length = 0;
} else if (length >= 2) {
enable = true;
length -= 2;
} else {
return -EINVAL;
}
if (length > INTEL_QEPFLT_MAX_COUNT(length))
return -ERANGE;
mutex_lock(&qep->lock);
if (qep->enabled) {
ret = -EBUSY;
goto out;
}
pm_runtime_get_sync(qep->dev);
reg = intel_qep_readl(qep, INTEL_QEPCON);
if (enable)
reg |= INTEL_QEPCON_FLT_EN;
else
reg &= ~INTEL_QEPCON_FLT_EN;
intel_qep_writel(qep, INTEL_QEPFLT, length);
intel_qep_writel(qep, INTEL_QEPCON, reg);
pm_runtime_put(qep->dev);
out:
mutex_unlock(&qep->lock);
return ret;
}