static int qat_hal_chip_init()

in qat/qat_common/qat_hal.c [682:819]

• 131 lines of code
• 6 McCabe index (conditional complexity)

static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
			     struct adf_accel_dev *accel_dev)
{
	struct adf_accel_pci *pci_info = &accel_dev->accel_pci_dev;
	struct adf_hw_device_data *hw_data = accel_dev->hw_device;
	void __iomem *pmisc_addr = adf_get_pmisc_base(accel_dev);
	unsigned int max_en_ae_id = 0;
	struct adf_bar *sram_bar;
	unsigned int csr_val = 0;
	unsigned long ae_mask;
	unsigned char ae = 0;
	int ret = 0;

	handle->pci_dev = pci_info->pci_dev;
	switch (handle->pci_dev->device) {
	case ADF_4XXX_PCI_DEVICE_ID:
		handle->chip_info->mmp_sram_size = 0;
		handle->chip_info->nn = false;
		handle->chip_info->lm2lm3 = true;
		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X;
		handle->chip_info->icp_rst_csr = ICP_RESET_CPP0;
		handle->chip_info->icp_rst_mask = 0x100015;
		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0;
		handle->chip_info->misc_ctl_csr = MISC_CONTROL_C4XXX;
		handle->chip_info->wakeup_event_val = 0x80000000;
		handle->chip_info->fw_auth = true;
		handle->chip_info->css_3k = true;
		handle->chip_info->tgroup_share_ustore = true;
		handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX;
		handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;
		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI_4XXX;
		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO_4XXX;
		handle->chip_info->fcu_loaded_ae_csr = FCU_AE_LOADED_4XXX;
		handle->chip_info->fcu_loaded_ae_pos = 0;

		handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET_4XXX;
		handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET_4XXX;
		handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET_4XXX;
		handle->hal_cap_ae_local_csr_addr_v =
			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v
			+ LOCAL_TO_XFER_REG_OFFSET);
		break;
	case PCI_DEVICE_ID_INTEL_QAT_C62X:
	case PCI_DEVICE_ID_INTEL_QAT_C3XXX:
		handle->chip_info->mmp_sram_size = 0;
		handle->chip_info->nn = true;
		handle->chip_info->lm2lm3 = false;
		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
		handle->chip_info->icp_rst_csr = ICP_RESET;
		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |
						  (hw_data->accel_mask << RST_CSR_QAT_LSB);
		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
		handle->chip_info->fw_auth = true;
		handle->chip_info->css_3k = false;
		handle->chip_info->tgroup_share_ustore = false;
		handle->chip_info->fcu_ctl_csr = FCU_CONTROL;
		handle->chip_info->fcu_sts_csr = FCU_STATUS;
		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI;
		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO;
		handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS;
		handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS;
		handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET;
		handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET;
		handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET;
		handle->hal_cap_ae_local_csr_addr_v =
			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v
			+ LOCAL_TO_XFER_REG_OFFSET);
		break;
	case PCI_DEVICE_ID_INTEL_QAT_DH895XCC:
		handle->chip_info->mmp_sram_size = 0x40000;
		handle->chip_info->nn = true;
		handle->chip_info->lm2lm3 = false;
		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
		handle->chip_info->icp_rst_csr = ICP_RESET;
		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |
						  (hw_data->accel_mask << RST_CSR_QAT_LSB);
		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
		handle->chip_info->fw_auth = false;
		handle->chip_info->css_3k = false;
		handle->chip_info->tgroup_share_ustore = false;
		handle->chip_info->fcu_ctl_csr = 0;
		handle->chip_info->fcu_sts_csr = 0;
		handle->chip_info->fcu_dram_addr_hi = 0;
		handle->chip_info->fcu_dram_addr_lo = 0;
		handle->chip_info->fcu_loaded_ae_csr = 0;
		handle->chip_info->fcu_loaded_ae_pos = 0;
		handle->hal_cap_g_ctl_csr_addr_v = pmisc_addr + ICP_QAT_CAP_OFFSET;
		handle->hal_cap_ae_xfer_csr_addr_v = pmisc_addr + ICP_QAT_AE_OFFSET;
		handle->hal_ep_csr_addr_v = pmisc_addr + ICP_QAT_EP_OFFSET;
		handle->hal_cap_ae_local_csr_addr_v =
			(void __iomem *)((uintptr_t)handle->hal_cap_ae_xfer_csr_addr_v
			+ LOCAL_TO_XFER_REG_OFFSET);
		break;
	default:
		ret = -EINVAL;
		goto out_err;
	}

	if (handle->chip_info->mmp_sram_size > 0) {
		sram_bar =
			&pci_info->pci_bars[hw_data->get_sram_bar_id(hw_data)];
		handle->hal_sram_addr_v = sram_bar->virt_addr;
	}
	handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid;
	handle->hal_handle->ae_mask = hw_data->ae_mask;
	handle->hal_handle->admin_ae_mask = hw_data->admin_ae_mask;
	handle->hal_handle->slice_mask = hw_data->accel_mask;
	handle->cfg_ae_mask = ALL_AE_MASK;
	/* create AE objects */
	handle->hal_handle->upc_mask = 0x1ffff;
	handle->hal_handle->max_ustore = 0x4000;

	ae_mask = handle->hal_handle->ae_mask;
	for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) {
		handle->hal_handle->aes[ae].free_addr = 0;
		handle->hal_handle->aes[ae].free_size =
		    handle->hal_handle->max_ustore;
		handle->hal_handle->aes[ae].ustore_size =
		    handle->hal_handle->max_ustore;
		handle->hal_handle->aes[ae].live_ctx_mask =
						ICP_QAT_UCLO_AE_ALL_CTX;
		max_en_ae_id = ae;
	}
	handle->hal_handle->ae_max_num = max_en_ae_id + 1;

	/* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
		csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
		csr_val |= 0x1;
		qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);
	}
out_err:
	return ret;
}