static int socfpga_a10_fpga_probe()

in socfpga-a10.c [468:521]

• 42 lines of code
• 8 McCabe index (conditional complexity)

static int socfpga_a10_fpga_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct a10_fpga_priv *priv;
	void __iomem *reg_base;
	struct fpga_manager *mgr;
	struct resource *res;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	/* First mmio base is for register access */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(reg_base))
		return PTR_ERR(reg_base);

	/* Second mmio base is for writing FPGA image data */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	priv->fpga_data_addr = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->fpga_data_addr))
		return PTR_ERR(priv->fpga_data_addr);

	/* regmap for register access */
	priv->regmap = devm_regmap_init_mmio(dev, reg_base,
					     &socfpga_a10_fpga_regmap_config);
	if (IS_ERR(priv->regmap))
		return -ENODEV;

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(dev, "no clock specified\n");
		return PTR_ERR(priv->clk);
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret) {
		dev_err(dev, "could not enable clock\n");
		return -EBUSY;
	}

	mgr = fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
				&socfpga_a10_fpga_mgr_ops, priv);
	if (IS_ERR(mgr)) {
		clk_disable_unprepare(priv->clk);
		return PTR_ERR(mgr);
	}

	platform_set_drvdata(pdev, mgr);

	return 0;
}