static int fme_pr()

in dfl-fme-pr.c [66:163]

• 68 lines of code
• 11 McCabe index (conditional complexity)

static int fme_pr(struct platform_device *pdev, unsigned long arg)
{
	struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
	void __user *argp = (void __user *)arg;
	struct dfl_fpga_fme_port_pr port_pr;
	struct fpga_image_info *info;
	struct fpga_region *region;
	void __iomem *fme_hdr;
	struct dfl_fme *fme;
	unsigned long minsz;
	void *buf = NULL;
	size_t length;
	int ret = 0;
	u64 v;

	minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);

	if (copy_from_user(&port_pr, argp, minsz))
		return -EFAULT;

	if (port_pr.argsz < minsz || port_pr.flags)
		return -EINVAL;

	/* get fme header region */
	fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
					       FME_FEATURE_ID_HEADER);

	/* check port id */
	v = readq(fme_hdr + FME_HDR_CAP);
	if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
		dev_dbg(&pdev->dev, "port number more than maximum\n");
		return -EINVAL;
	}

	/*
	 * align PR buffer per PR bandwidth, as HW ignores the extra padding
	 * data automatically.
	 */
	length = ALIGN(port_pr.buffer_size, 4);

	buf = vmalloc(length);
	if (!buf)
		return -ENOMEM;

	if (copy_from_user(buf,
			   (void __user *)(unsigned long)port_pr.buffer_address,
			   port_pr.buffer_size)) {
		ret = -EFAULT;
		goto free_exit;
	}

	/* prepare fpga_image_info for PR */
	info = fpga_image_info_alloc(&pdev->dev);
	if (!info) {
		ret = -ENOMEM;
		goto free_exit;
	}

	info->flags |= FPGA_MGR_PARTIAL_RECONFIG;

	mutex_lock(&pdata->lock);
	fme = dfl_fpga_pdata_get_private(pdata);
	/* fme device has been unregistered. */
	if (!fme) {
		ret = -EINVAL;
		goto unlock_exit;
	}

	region = dfl_fme_region_find(fme, port_pr.port_id);
	if (!region) {
		ret = -EINVAL;
		goto unlock_exit;
	}

	fpga_image_info_free(region->info);

	info->buf = buf;
	info->count = length;
	info->region_id = port_pr.port_id;
	region->info = info;

	ret = fpga_region_program_fpga(region);

	/*
	 * it allows userspace to reset the PR region's logic by disabling and
	 * reenabling the bridge to clear things out between acceleration runs.
	 * so no need to hold the bridges after partial reconfiguration.
	 */
	if (region->get_bridges)
		fpga_bridges_put(&region->bridge_list);

	put_device(&region->dev);
unlock_exit:
	mutex_unlock(&pdata->lock);
free_exit:
	vfree(buf);
	return ret;
}