in w83627ehf.c [1695:1945]
static int __init w83627ehf_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct w83627ehf_sio_data *sio_data = dev_get_platdata(dev);
struct w83627ehf_data *data;
struct resource *res;
u8 en_vrm10;
int i, err = 0;
struct device *hwmon_dev;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!devm_request_region(dev, res->start, IOREGION_LENGTH, DRVNAME))
return -EBUSY;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->addr = res->start;
mutex_init(&data->lock);
mutex_init(&data->update_lock);
data->name = w83627ehf_device_names[sio_data->kind];
data->bank = 0xff; /* Force initial bank selection */
platform_set_drvdata(pdev, data);
/* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
/* 667HG has 3 pwms, and 627UHG has only 2 */
switch (sio_data->kind) {
default:
data->pwm_num = 4;
break;
case w83667hg:
case w83667hg_b:
data->pwm_num = 3;
break;
case w83627uhg:
data->pwm_num = 2;
break;
}
/* Default to 3 temperature inputs, code below will adjust as needed */
data->have_temp = 0x07;
/* Deal with temperature register setup first. */
if (sio_data->kind == w83667hg_b) {
u8 reg;
w83627ehf_set_temp_reg_ehf(data, 4);
/*
* Temperature sources are selected with bank 0, registers 0x49
* and 0x4a.
*/
reg = w83627ehf_read_value(data, 0x4a);
data->temp_src[0] = reg >> 5;
reg = w83627ehf_read_value(data, 0x49);
data->temp_src[1] = reg & 0x07;
data->temp_src[2] = (reg >> 4) & 0x07;
/*
* W83667HG-B has another temperature register at 0x7e.
* The temperature source is selected with register 0x7d.
* Support it if the source differs from already reported
* sources.
*/
reg = w83627ehf_read_value(data, 0x7d);
reg &= 0x07;
if (reg != data->temp_src[0] && reg != data->temp_src[1]
&& reg != data->temp_src[2]) {
data->temp_src[3] = reg;
data->have_temp |= 1 << 3;
}
/*
* Chip supports either AUXTIN or VIN3. Try to find out which
* one.
*/
reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
if (data->temp_src[2] == 2 && (reg & 0x01))
data->have_temp &= ~(1 << 2);
if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
|| (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
data->in6_skip = 1;
data->temp_label = w83667hg_b_temp_label;
data->have_temp_offset = data->have_temp & 0x07;
for (i = 0; i < 3; i++) {
if (data->temp_src[i] > 2)
data->have_temp_offset &= ~(1 << i);
}
} else if (sio_data->kind == w83627uhg) {
u8 reg;
w83627ehf_set_temp_reg_ehf(data, 3);
/*
* Temperature sources for temp2 and temp3 are selected with
* bank 0, registers 0x49 and 0x4a.
*/
data->temp_src[0] = 0; /* SYSTIN */
reg = w83627ehf_read_value(data, 0x49) & 0x07;
/* Adjust to have the same mapping as other source registers */
if (reg == 0)
data->temp_src[1] = 1;
else if (reg >= 2 && reg <= 5)
data->temp_src[1] = reg + 2;
else /* should never happen */
data->have_temp &= ~(1 << 1);
reg = w83627ehf_read_value(data, 0x4a);
data->temp_src[2] = reg >> 5;
/*
* Skip temp3 if source is invalid or the same as temp1
* or temp2.
*/
if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
data->temp_src[2] == data->temp_src[0] ||
((data->have_temp & (1 << 1)) &&
data->temp_src[2] == data->temp_src[1]))
data->have_temp &= ~(1 << 2);
else
data->temp3_val_only = 1; /* No limit regs */
data->in6_skip = 1; /* No VIN3 */
data->temp_label = w83667hg_b_temp_label;
data->have_temp_offset = data->have_temp & 0x03;
for (i = 0; i < 3; i++) {
if (data->temp_src[i] > 1)
data->have_temp_offset &= ~(1 << i);
}
} else {
w83627ehf_set_temp_reg_ehf(data, 3);
/* Temperature sources are fixed */
if (sio_data->kind == w83667hg) {
u8 reg;
/*
* Chip supports either AUXTIN or VIN3. Try to find
* out which one.
*/
reg = w83627ehf_read_value(data,
W83627EHF_REG_TEMP_CONFIG[2]);
if (reg & 0x01)
data->have_temp &= ~(1 << 2);
else
data->in6_skip = 1;
}
data->have_temp_offset = data->have_temp & 0x07;
}
if (sio_data->kind == w83667hg_b) {
data->REG_FAN_MAX_OUTPUT =
W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
data->REG_FAN_STEP_OUTPUT =
W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
} else {
data->REG_FAN_MAX_OUTPUT =
W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
data->REG_FAN_STEP_OUTPUT =
W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
}
/* Setup input voltage scaling factors */
if (sio_data->kind == w83627uhg)
data->scale_in = scale_in_w83627uhg;
else
data->scale_in = scale_in_common;
/* Initialize the chip */
w83627ehf_init_device(data, sio_data->kind);
data->vrm = vid_which_vrm();
err = superio_enter(sio_data->sioreg);
if (err)
return err;
/* Read VID value */
if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
/*
* W83667HG has different pins for VID input and output, so
* we can get the VID input values directly at logical device D
* 0xe3.
*/
superio_select(sio_data->sioreg, W83667HG_LD_VID);
data->vid = superio_inb(sio_data->sioreg, 0xe3);
data->have_vid = true;
} else if (sio_data->kind != w83627uhg) {
superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
/*
* Set VID input sensibility if needed. In theory the
* BIOS should have set it, but in practice it's not
* always the case. We only do it for the W83627EHF/EHG
* because the W83627DHG is more complex in this
* respect.
*/
if (sio_data->kind == w83627ehf) {
en_vrm10 = superio_inb(sio_data->sioreg,
SIO_REG_EN_VRM10);
if ((en_vrm10 & 0x08) && data->vrm == 90) {
dev_warn(dev,
"Setting VID input voltage to TTL\n");
superio_outb(sio_data->sioreg,
SIO_REG_EN_VRM10,
en_vrm10 & ~0x08);
} else if (!(en_vrm10 & 0x08)
&& data->vrm == 100) {
dev_warn(dev,
"Setting VID input voltage to VRM10\n");
superio_outb(sio_data->sioreg,
SIO_REG_EN_VRM10,
en_vrm10 | 0x08);
}
}
data->vid = superio_inb(sio_data->sioreg,
SIO_REG_VID_DATA);
if (sio_data->kind == w83627ehf) /* 6 VID pins only */
data->vid &= 0x3f;
data->have_vid = true;
} else {
dev_info(dev,
"VID pins in output mode, CPU VID not available\n");
}
}
w83627ehf_check_fan_inputs(sio_data, data);
superio_exit(sio_data->sioreg);
/* Read fan clock dividers immediately */
w83627ehf_update_fan_div(data);
/* Read pwm data to save original values */
w83627ehf_update_pwm(data);
for (i = 0; i < data->pwm_num; i++)
data->pwm_enable_orig[i] = data->pwm_enable[i];
hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev,
data->name,
data,
&w83627ehf_chip_info,
w83627ehf_groups);
return PTR_ERR_OR_ZERO(hwmon_dev);
}