in busses/i2c-qup.c [1657:1905]
static int qup_i2c_probe(struct platform_device *pdev)
{
static const int blk_sizes[] = {4, 16, 32};
struct qup_i2c_dev *qup;
unsigned long one_bit_t;
u32 io_mode, hw_ver, size;
int ret, fs_div, hs_div;
u32 src_clk_freq = DEFAULT_SRC_CLK;
u32 clk_freq = DEFAULT_CLK_FREQ;
int blocks;
bool is_qup_v1;
qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
if (!qup)
return -ENOMEM;
qup->dev = &pdev->dev;
init_completion(&qup->xfer);
platform_set_drvdata(pdev, qup);
if (scl_freq) {
dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
clk_freq = scl_freq;
} else {
ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
if (ret) {
dev_notice(qup->dev, "using default clock-frequency %d",
DEFAULT_CLK_FREQ);
}
}
if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
qup->adap.algo = &qup_i2c_algo;
qup->adap.quirks = &qup_i2c_quirks;
is_qup_v1 = true;
} else {
qup->adap.algo = &qup_i2c_algo_v2;
qup->adap.quirks = &qup_i2c_quirks_v2;
is_qup_v1 = false;
if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
goto nodma;
else
ret = qup_i2c_req_dma(qup);
if (ret == -EPROBE_DEFER)
goto fail_dma;
else if (ret != 0)
goto nodma;
qup->max_xfer_sg_len = (MX_BLOCKS << 1);
blocks = (MX_DMA_BLOCKS << 1) + 1;
qup->btx.sg = devm_kcalloc(&pdev->dev,
blocks, sizeof(*qup->btx.sg),
GFP_KERNEL);
if (!qup->btx.sg) {
ret = -ENOMEM;
goto fail_dma;
}
sg_init_table(qup->btx.sg, blocks);
qup->brx.sg = devm_kcalloc(&pdev->dev,
blocks, sizeof(*qup->brx.sg),
GFP_KERNEL);
if (!qup->brx.sg) {
ret = -ENOMEM;
goto fail_dma;
}
sg_init_table(qup->brx.sg, blocks);
/* 2 tag bytes for each block + 5 for start, stop tags */
size = blocks * 2 + 5;
qup->start_tag.start = devm_kzalloc(&pdev->dev,
size, GFP_KERNEL);
if (!qup->start_tag.start) {
ret = -ENOMEM;
goto fail_dma;
}
qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
if (!qup->brx.tag.start) {
ret = -ENOMEM;
goto fail_dma;
}
qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
if (!qup->btx.tag.start) {
ret = -ENOMEM;
goto fail_dma;
}
qup->is_dma = true;
}
nodma:
/* We support frequencies up to FAST Mode Plus (1MHz) */
if (!clk_freq || clk_freq > I2C_MAX_FAST_MODE_PLUS_FREQ) {
dev_err(qup->dev, "clock frequency not supported %d\n",
clk_freq);
return -EINVAL;
}
qup->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(qup->base))
return PTR_ERR(qup->base);
qup->irq = platform_get_irq(pdev, 0);
if (qup->irq < 0)
return qup->irq;
if (has_acpi_companion(qup->dev)) {
ret = device_property_read_u32(qup->dev,
"src-clock-hz", &src_clk_freq);
if (ret) {
dev_notice(qup->dev, "using default src-clock-hz %d",
DEFAULT_SRC_CLK);
}
ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
} else {
qup->clk = devm_clk_get(qup->dev, "core");
if (IS_ERR(qup->clk)) {
dev_err(qup->dev, "Could not get core clock\n");
return PTR_ERR(qup->clk);
}
qup->pclk = devm_clk_get(qup->dev, "iface");
if (IS_ERR(qup->pclk)) {
dev_err(qup->dev, "Could not get iface clock\n");
return PTR_ERR(qup->pclk);
}
qup_i2c_enable_clocks(qup);
src_clk_freq = clk_get_rate(qup->clk);
}
/*
* Bootloaders might leave a pending interrupt on certain QUP's,
* so we reset the core before registering for interrupts.
*/
writel(1, qup->base + QUP_SW_RESET);
ret = qup_i2c_poll_state_valid(qup);
if (ret)
goto fail;
ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
"i2c_qup", qup);
if (ret) {
dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
goto fail;
}
hw_ver = readl(qup->base + QUP_HW_VERSION);
dev_dbg(qup->dev, "Revision %x\n", hw_ver);
io_mode = readl(qup->base + QUP_IO_MODE);
/*
* The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
* associated with each byte written/received
*/
size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
if (size >= ARRAY_SIZE(blk_sizes)) {
ret = -EIO;
goto fail;
}
qup->out_blk_sz = blk_sizes[size];
size = QUP_INPUT_BLOCK_SIZE(io_mode);
if (size >= ARRAY_SIZE(blk_sizes)) {
ret = -EIO;
goto fail;
}
qup->in_blk_sz = blk_sizes[size];
if (is_qup_v1) {
/*
* in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
* single transfer but the block size is in bytes so divide the
* in_blk_sz and out_blk_sz by 2
*/
qup->in_blk_sz /= 2;
qup->out_blk_sz /= 2;
qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
} else {
qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
}
size = QUP_OUTPUT_FIFO_SIZE(io_mode);
qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
size = QUP_INPUT_FIFO_SIZE(io_mode);
qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
hs_div = 3;
if (clk_freq <= I2C_MAX_STANDARD_MODE_FREQ) {
fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
} else {
/* 33%/66% duty cycle */
fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
}
/*
* Time it takes for a byte to be clocked out on the bus.
* Each byte takes 9 clock cycles (8 bits + 1 ack).
*/
one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
qup->one_byte_t = one_bit_t * 9;
qup->xfer_timeout = TOUT_MIN * HZ +
usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
qup->in_blk_sz, qup->in_fifo_sz,
qup->out_blk_sz, qup->out_fifo_sz);
i2c_set_adapdata(&qup->adap, qup);
qup->adap.dev.parent = qup->dev;
qup->adap.dev.of_node = pdev->dev.of_node;
qup->is_last = true;
strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
pm_runtime_use_autosuspend(qup->dev);
pm_runtime_set_active(qup->dev);
pm_runtime_enable(qup->dev);
ret = i2c_add_adapter(&qup->adap);
if (ret)
goto fail_runtime;
return 0;
fail_runtime:
pm_runtime_disable(qup->dev);
pm_runtime_set_suspended(qup->dev);
fail:
qup_i2c_disable_clocks(qup);
fail_dma:
if (qup->btx.dma)
dma_release_channel(qup->btx.dma);
if (qup->brx.dma)
dma_release_channel(qup->brx.dma);
return ret;
}