in dvb-frontends/drx39xyj/drxj.c [5712:6209]
static int set_vsb(struct drx_demod_instance *demod)
{
struct i2c_device_addr *dev_addr = NULL;
int rc;
struct drx_common_attr *common_attr = NULL;
struct drxjscu_cmd cmd_scu;
struct drxj_data *ext_attr = NULL;
u16 cmd_result = 0;
u16 cmd_param = 0;
static const u8 vsb_taps_re[] = {
DRXJ_16TO8(-2), /* re0 */
DRXJ_16TO8(4), /* re1 */
DRXJ_16TO8(1), /* re2 */
DRXJ_16TO8(-4), /* re3 */
DRXJ_16TO8(1), /* re4 */
DRXJ_16TO8(4), /* re5 */
DRXJ_16TO8(-3), /* re6 */
DRXJ_16TO8(-3), /* re7 */
DRXJ_16TO8(6), /* re8 */
DRXJ_16TO8(1), /* re9 */
DRXJ_16TO8(-9), /* re10 */
DRXJ_16TO8(3), /* re11 */
DRXJ_16TO8(12), /* re12 */
DRXJ_16TO8(-9), /* re13 */
DRXJ_16TO8(-15), /* re14 */
DRXJ_16TO8(17), /* re15 */
DRXJ_16TO8(19), /* re16 */
DRXJ_16TO8(-29), /* re17 */
DRXJ_16TO8(-22), /* re18 */
DRXJ_16TO8(45), /* re19 */
DRXJ_16TO8(25), /* re20 */
DRXJ_16TO8(-70), /* re21 */
DRXJ_16TO8(-28), /* re22 */
DRXJ_16TO8(111), /* re23 */
DRXJ_16TO8(30), /* re24 */
DRXJ_16TO8(-201), /* re25 */
DRXJ_16TO8(-31), /* re26 */
DRXJ_16TO8(629) /* re27 */
};
dev_addr = demod->my_i2c_dev_addr;
common_attr = (struct drx_common_attr *) demod->my_common_attr;
ext_attr = (struct drxj_data *) demod->my_ext_attr;
/* stop all comm_exec */
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* reset demodulator */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_RESET;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* set higher threshold */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* burst detection on */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* drop thresholds by 1 dB */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* drop thresholds by 2 dB */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* cma on */
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* GPIO */
/* Initialize the FEC Subsystem */
rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
u16 fec_oc_snc_mode = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* output data even when not locked */
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* set clip */
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* no transparent, no A&C framing; parity is set in mpegoutput */
{
u16 fec_oc_reg_mode = 0;
rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* timeout counter for restarting */
rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
} /* bypass disabled */
/* initialize RS packet error measurement parameters */
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* init measurement period of MER/SER */
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* B-Input to ADC, PGA+filter in standby */
if (!ext_attr->has_lna) {
rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* turn on IQMAF. It has to be in front of setAgc**() */
rc = set_iqm_af(demod, true);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = adc_synchronization(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = init_agc(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
of only the gain */
struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* Mpeg output has to be in front of FEC active */
rc = set_mpegtei_handling(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = bit_reverse_mpeg_output(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = set_mpeg_start_width(demod);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
{
/* TODO: move to set_standard after hardware reset value problem is solved */
/* Configure initial MPEG output */
struct drx_cfg_mpeg_output cfg_mpeg_output;
memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
cfg_mpeg_output.enable_mpeg_output = true;
rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
}
/* TBD: what parameters should be set */
cmd_param = 0x00; /* Default mode AGC on, etc */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
cmd_scu.parameter_len = 1;
cmd_scu.result_len = 1;
cmd_scu.parameter = &cmd_param;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
/* start demodulator */
cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
| SCU_RAM_COMMAND_CMD_DEMOD_START;
cmd_scu.parameter_len = 0;
cmd_scu.result_len = 1;
cmd_scu.parameter = NULL;
cmd_scu.result = &cmd_result;
rc = scu_command(dev_addr, &cmd_scu);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
if (rc != 0) {
pr_err("error %d\n", rc);
goto rw_error;
}
return 0;
rw_error:
return rc;
}