in habanalabs/goya/goya_security.c [28:270]
static void goya_init_mme_protection_bits(struct hl_device *hdev)
{
u32 pb_addr, mask;
u8 word_offset;
/* TODO: change to real reg name when Soc Online is updated */
u64 mmMME_SBB_POWER_ECO1 = 0xDFF60,
mmMME_SBB_POWER_ECO2 = 0xDFF64;
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_0_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_1_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_2_BASE);
goya_pb_set_block(hdev, mmACC_MS_ECC_MEM_3_BASE);
goya_pb_set_block(hdev, mmSBA_ECC_MEM_BASE);
goya_pb_set_block(hdev, mmSBB_ECC_MEM_BASE);
goya_pb_set_block(hdev, mmMME1_RTR_BASE);
goya_pb_set_block(hdev, mmMME1_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME1_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME2_RTR_BASE);
goya_pb_set_block(hdev, mmMME2_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME2_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME3_RTR_BASE);
goya_pb_set_block(hdev, mmMME3_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME3_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME4_RTR_BASE);
goya_pb_set_block(hdev, mmMME4_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME4_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME5_RTR_BASE);
goya_pb_set_block(hdev, mmMME5_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME5_WR_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME6_RTR_BASE);
goya_pb_set_block(hdev, mmMME6_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmMME6_WR_REGULATOR_BASE);
pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_DUMMY & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2);
mask |= 1 << ((mmMME_RESET & 0x7F) >> 2);
mask |= 1 << ((mmMME_STALL & 0x7F) >> 2);
mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2);
mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2);
mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2);
mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2);
mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2);
mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2);
mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2);
mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_STORE_MAX_CREDIT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_STORE_MAX_CREDIT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2);
mask |= 1 << ((mmMME_AGU & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBA & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBB & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBC & 0x7F) >> 2);
mask |= 1 << ((mmMME_WBC & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_TE & 0x7F) >> 2);
mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2);
mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2);
mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2);
mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2);
mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2);
mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2);
mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_QM_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_QM_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_QM_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_QM_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_QM_CP_STS & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_QM_CP_STS & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2);
mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_CMDQ_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_CMDQ_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_CMDQ_CQ_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_CMDQ_CQ_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_CMDQ_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_CMDQ_CQ_IFIFO_CNT &
PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_CMDQ_CP_CURRENT_INST_HI & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_CMDQ_CP_CURRENT_INST_HI & PROT_BITS_OFFS) >> 7)
<< 2;
mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2);
mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmMME_SBB_POWER_ECO1 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmMME_SBB_POWER_ECO1 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2);
mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
}