in habanalabs/goya/goya_security.c [2380:3122]
void goya_init_security(struct hl_device *hdev)
{
struct goya_device *goya = hdev->asic_specific;
u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE);
u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE);
u32 lbw_rng0_base = 0xFC440000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng0_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng1_base = 0xFC480000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng1_mask = 0xFFF80000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng2_base = 0xFC600000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng2_mask = 0xFFE00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng3_base = 0xFC800000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng3_mask = 0xFFF00000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng4_base = 0xFCC02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng4_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng5_base = 0xFCC40000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng5_mask = 0xFFFF8000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng6_base = 0xFCC48000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng6_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng7_base = 0xFCC4A000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng7_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng8_base = 0xFCC4C000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng8_mask = 0xFFFFC000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng9_base = 0xFCC50000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng9_mask = 0xFFFF0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng10_base = 0xFCC60000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng10_mask = 0xFFFE0000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng11_base = 0xFCE02000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng11_mask = 0xFFFFE000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng12_base = 0xFE484000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng12_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng13_base = 0xFEC43000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
u32 lbw_rng13_mask = 0xFFFFF000 & DMA_MACRO_LBW_RANGE_BASE_R_MASK;
WREG32(mmDMA_MACRO_LBW_RANGE_HIT_BLOCK, 0xFFFF);
WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFF);
if (!(goya->hw_cap_initialized & HW_CAP_MMU)) {
WREG32(mmDMA_MACRO_HBW_RANGE_HIT_BLOCK, 0xFE);
/* Protect HOST */
WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_0, 0);
WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_0, 0);
WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_0, 0);
WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_0, 0xFFF80);
}
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmDMA_MACRO_HBW_RANGE_BASE_31_0_1, dram_addr_lo);
WREG32(mmDMA_MACRO_HBW_RANGE_BASE_49_32_1, dram_addr_hi);
WREG32(mmDMA_MACRO_HBW_RANGE_MASK_31_0_1, 0xE0000000);
WREG32(mmDMA_MACRO_HBW_RANGE_MASK_49_32_1, 0x3FFFF);
/* Protect registers */
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmDMA_MACRO_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmDMA_MACRO_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME1_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME2_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME3_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME4_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME5_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME6_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmMME1_RTR_HBW_RANGE_HIT, 0xFE);
WREG32(mmMME2_RTR_HBW_RANGE_HIT, 0xFE);
WREG32(mmMME3_RTR_HBW_RANGE_HIT, 0xFE);
WREG32(mmMME4_RTR_HBW_RANGE_HIT, 0xFE);
WREG32(mmMME5_RTR_HBW_RANGE_HIT, 0xFE);
WREG32(mmMME6_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmMME1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmMME6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmMME6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmMME6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmMME6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmMME6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC0_NRTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC0_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC0_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC0_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC0_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC1_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC1_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC1_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC1_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC1_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC1_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC1_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC2_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC2_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC2_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC2_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC2_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC2_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC2_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC3_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC3_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC3_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC3_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC3_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC3_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC3_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC4_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC4_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC4_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC4_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC4_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC4_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC4_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC5_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC5_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC5_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC5_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC5_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC5_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC5_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC6_RTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC6_RTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC6_RTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC6_RTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC6_RTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC6_RTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC6_RTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_HIT, 0xFFFF);
WREG32(mmTPC7_NRTR_HBW_RANGE_HIT, 0xFE);
/* Protect HOST */
WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_0, 0);
WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_0, 0);
WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_0, 0);
WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_0, 0xFFF80);
/*
* Protect DDR @
* DRAM_VIRT_BASE : DRAM_VIRT_BASE + DRAM_VIRT_END
* The mask protects the first 512MB
*/
WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_L_1, dram_addr_lo);
WREG32(mmTPC7_NRTR_HBW_RANGE_BASE_H_1, dram_addr_hi);
WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_L_1, 0xE0000000);
WREG32(mmTPC7_NRTR_HBW_RANGE_MASK_H_1, 0x3FFFF);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_0, lbw_rng0_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_0, lbw_rng0_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_1, lbw_rng1_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_1, lbw_rng1_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_2, lbw_rng2_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_2, lbw_rng2_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_3, lbw_rng3_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_3, lbw_rng3_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_4, lbw_rng4_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_4, lbw_rng4_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_5, lbw_rng5_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_5, lbw_rng5_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_6, lbw_rng6_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_6, lbw_rng6_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_7, lbw_rng7_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_7, lbw_rng7_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_8, lbw_rng8_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_8, lbw_rng8_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_9, lbw_rng9_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_9, lbw_rng9_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_10, lbw_rng10_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_10, lbw_rng10_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_11, lbw_rng11_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_11, lbw_rng11_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_12, lbw_rng12_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_12, lbw_rng12_mask);
WREG32(mmTPC7_NRTR_LBW_RANGE_BASE_13, lbw_rng13_base);
WREG32(mmTPC7_NRTR_LBW_RANGE_MASK_13, lbw_rng13_mask);
goya_init_protection_bits(hdev);
}