in habanalabs/goya/goya_security.c [272:670]
static void goya_init_dma_protection_bits(struct hl_device *hdev)
{
u32 pb_addr, mask;
u8 word_offset;
goya_pb_set_block(hdev, mmDMA_NRTR_BASE);
goya_pb_set_block(hdev, mmDMA_RD_REGULATOR_BASE);
goya_pb_set_block(hdev, mmDMA_WR_REGULATOR_BASE);
pb_addr = (mmDMA_QM_0_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_0_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_0_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_0_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_0_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_0_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
goya_pb_set_block(hdev, mmDMA_CH_0_BASE);
pb_addr = (mmDMA_QM_1_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_1_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_1_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_1_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_1_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_1_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
goya_pb_set_block(hdev, mmDMA_CH_1_BASE);
pb_addr = (mmDMA_QM_2_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_2_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_2_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_2_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_2_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_2_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
goya_pb_set_block(hdev, mmDMA_CH_2_BASE);
pb_addr = (mmDMA_QM_3_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_3_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_3_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_3_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_3_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_3_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
goya_pb_set_block(hdev, mmDMA_CH_3_BASE);
pb_addr = (mmDMA_QM_4_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_4_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_4_PQ_PUSH0 & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_4_PQ_PUSH0 & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
pb_addr = (mmDMA_QM_4_CQ_IFIFO_CNT & ~0xFFF) + PROT_BITS_OFFS;
word_offset = ((mmDMA_QM_4_CQ_IFIFO_CNT & PROT_BITS_OFFS) >> 7) << 2;
mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2);
mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2);
WREG32(pb_addr + word_offset, ~mask);
goya_pb_set_block(hdev, mmDMA_CH_4_BASE);
}