in wireless/realtek/rtlwifi/rtl8821ae/phy.c [2736:3143]
static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
u8 power_index, u8 path, u8 rate)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (path == RF90_PATH_A) {
switch (rate) {
case DESC_RATE1M:
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
MASKBYTE0, power_index);
break;
case DESC_RATE2M:
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
MASKBYTE1, power_index);
break;
case DESC_RATE5_5M:
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
MASKBYTE2, power_index);
break;
case DESC_RATE11M:
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
MASKBYTE3, power_index);
break;
case DESC_RATE6M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
MASKBYTE0, power_index);
break;
case DESC_RATE9M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
MASKBYTE1, power_index);
break;
case DESC_RATE12M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
MASKBYTE2, power_index);
break;
case DESC_RATE18M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
MASKBYTE3, power_index);
break;
case DESC_RATE24M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
MASKBYTE0, power_index);
break;
case DESC_RATE36M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
MASKBYTE1, power_index);
break;
case DESC_RATE48M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
MASKBYTE2, power_index);
break;
case DESC_RATE54M:
rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS0:
rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS1:
rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS2:
rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS3:
rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS4:
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS5:
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS6:
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS7:
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS8:
rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS9:
rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS10:
rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS11:
rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS12:
rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS13:
rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS14:
rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS15:
rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS0:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS1:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT1SS_MCS2:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT1SS_MCS3:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS4:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS5:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT1SS_MCS6:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT1SS_MCS7:
rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS8:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS9:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS0:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS1:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT2SS_MCS2:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT2SS_MCS3:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS4:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS5:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT2SS_MCS6:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT2SS_MCS7:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS8:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS9:
rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
MASKBYTE3, power_index);
break;
default:
rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
"Invalid Rate!!\n");
break;
}
} else if (path == RF90_PATH_B) {
switch (rate) {
case DESC_RATE1M:
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
MASKBYTE0, power_index);
break;
case DESC_RATE2M:
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
MASKBYTE1, power_index);
break;
case DESC_RATE5_5M:
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
MASKBYTE2, power_index);
break;
case DESC_RATE11M:
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
MASKBYTE3, power_index);
break;
case DESC_RATE6M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
MASKBYTE0, power_index);
break;
case DESC_RATE9M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
MASKBYTE1, power_index);
break;
case DESC_RATE12M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
MASKBYTE2, power_index);
break;
case DESC_RATE18M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
MASKBYTE3, power_index);
break;
case DESC_RATE24M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
MASKBYTE0, power_index);
break;
case DESC_RATE36M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
MASKBYTE1, power_index);
break;
case DESC_RATE48M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
MASKBYTE2, power_index);
break;
case DESC_RATE54M:
rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS0:
rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS1:
rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS2:
rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS3:
rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS4:
rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS5:
rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS6:
rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS7:
rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS8:
rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS9:
rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS10:
rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS11:
rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
MASKBYTE3, power_index);
break;
case DESC_RATEMCS12:
rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
MASKBYTE0, power_index);
break;
case DESC_RATEMCS13:
rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
MASKBYTE1, power_index);
break;
case DESC_RATEMCS14:
rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
MASKBYTE2, power_index);
break;
case DESC_RATEMCS15:
rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS0:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS1:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT1SS_MCS2:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT1SS_MCS3:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS4:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS5:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT1SS_MCS6:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT1SS_MCS7:
rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT1SS_MCS8:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT1SS_MCS9:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS0:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS1:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT2SS_MCS2:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT2SS_MCS3:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS4:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS5:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
MASKBYTE3, power_index);
break;
case DESC_RATEVHT2SS_MCS6:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
MASKBYTE0, power_index);
break;
case DESC_RATEVHT2SS_MCS7:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
MASKBYTE1, power_index);
break;
case DESC_RATEVHT2SS_MCS8:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
MASKBYTE2, power_index);
break;
case DESC_RATEVHT2SS_MCS9:
rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
MASKBYTE3, power_index);
break;
default:
rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
"Invalid Rate!!\n");
break;
}
} else {
rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
"Invalid RFPath!!\n");
}
}