in microchip/sparx5_serdes.c [942:1400]
static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd25g28_params *params)
{
struct sparx5_serdes_private *priv = macro->priv;
void __iomem **regs = priv->regs;
struct device *dev = priv->dev;
u32 sd_index = macro->stpidx;
u32 value;
sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
priv,
SD_LANE_25G_SD_LANE_CFG(sd_index));
sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
priv,
SD25G_LANE_CMU_FF(sd_index));
sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
(params->r_d_width_ctrl_from_hwt) |
SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
SD25G_LANE_CMU_1A_R_REG_MANUAL,
priv,
SD25G_LANE_CMU_1A(sd_index));
sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
(params->cfg_common_reserve_7_0),
SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
priv,
SD25G_LANE_CMU_31(sd_index));
sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
SD25G_LANE_CMU_09_CFG_EN_DUMMY,
priv,
SD25G_LANE_CMU_09(sd_index));
sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET
(params->cfg_pll_reserve_3_0),
SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
priv,
SD25G_LANE_CMU_13(sd_index));
sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
priv,
SD25G_LANE_CMU_40(sd_index));
sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
(params->l0_cfg_tx_reserve_15_8),
SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
priv,
SD25G_LANE_CMU_46(sd_index));
sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET
(params->l0_cfg_tx_reserve_7_0),
SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
priv,
SD25G_LANE_CMU_45(sd_index));
sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
priv,
SD25G_LANE_CMU_0B(sd_index));
sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
priv,
SD25G_LANE_CMU_0B(sd_index));
sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
SD25G_LANE_CMU_19_R_CK_RESETB,
priv,
SD25G_LANE_CMU_19(sd_index));
sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
SD25G_LANE_CMU_19_R_CK_RESETB,
priv,
SD25G_LANE_CMU_19(sd_index));
sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0),
SD25G_LANE_CMU_18_R_PLL_RSTN,
priv,
SD25G_LANE_CMU_18(sd_index));
sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1),
SD25G_LANE_CMU_18_R_PLL_RSTN,
priv,
SD25G_LANE_CMU_18(sd_index));
sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0),
SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0,
priv,
SD25G_LANE_CMU_1A(sd_index));
sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET
(params->r_txfifo_ck_div_pmad_2_0) |
SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET
(params->r_rxfifo_ck_div_pmad_2_0),
SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 |
SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0,
priv,
SD25G_LANE_CMU_30(sd_index));
sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) |
SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET
(params->cfg_vco_div_mode_1_0),
SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET |
SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0,
priv,
SD25G_LANE_CMU_0C(sd_index));
sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET
(params->cfg_pre_divsel_1_0),
SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0,
priv,
SD25G_LANE_CMU_0D(sd_index));
sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0),
SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0,
priv,
SD25G_LANE_CMU_0E(sd_index));
sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00),
SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
priv,
SD25G_LANE_CMU_FF(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
(params->cfg_pma_tx_ck_bitwidth_2_0),
SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0,
priv,
SD25G_LANE_LANE_0C(sd_index));
sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET
(params->cfg_tx_prediv_1_0),
SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0,
priv,
SD25G_LANE_LANE_01(sd_index));
sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET
(params->cfg_rxdiv_sel_2_0),
SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0,
priv,
SD25G_LANE_LANE_18(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET
(params->cfg_tx_subrate_2_0),
SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0,
priv,
SD25G_LANE_LANE_2C(sd_index));
sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET
(params->cfg_rx_subrate_2_0),
SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0,
priv,
SD25G_LANE_LANE_28(sd_index));
sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN,
priv,
SD25G_LANE_LANE_18(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET
(params->cfg_dfetap_en_5_1),
SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1,
priv,
SD25G_LANE_LANE_0F(sd_index));
sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
priv,
SD25G_LANE_LANE_18(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en),
SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN,
priv,
SD25G_LANE_LANE_1D(sd_index));
sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd),
SD25G_LANE_LANE_19_LN_CFG_ECDR_PD,
priv,
SD25G_LANE_LANE_19(sd_index));
sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET
(params->cfg_itx_ipdriver_base_2_0),
SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0,
priv,
SD25G_LANE_LANE_01(sd_index));
sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0),
SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0,
priv,
SD25G_LANE_LANE_03(sd_index));
sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0),
SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0,
priv,
SD25G_LANE_LANE_06(sd_index));
sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) |
SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly),
SD25G_LANE_LANE_07_LN_CFG_EN_ADV |
SD25G_LANE_LANE_07_LN_CFG_EN_DLY,
priv,
SD25G_LANE_LANE_07(sd_index));
sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET
(params->cfg_tx_reserve_15_8),
SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8,
priv,
SD25G_LANE_LANE_43(sd_index));
sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET
(params->cfg_tx_reserve_7_0),
SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0,
priv,
SD25G_LANE_LANE_42(sd_index));
sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0),
SD25G_LANE_LANE_05_LN_CFG_BW_1_0,
priv,
SD25G_LANE_LANE_05(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET
(params->cfg_txcal_man_en),
SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN,
priv,
SD25G_LANE_LANE_0B(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET
(params->cfg_txcal_shift_code_5_0),
SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0,
priv,
SD25G_LANE_LANE_0A(sd_index));
sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET
(params->cfg_txcal_valid_sel_3_0),
SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0,
priv,
SD25G_LANE_LANE_09(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0),
SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0,
priv,
SD25G_LANE_LANE_1A(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0),
SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0,
priv,
SD25G_LANE_LANE_1B(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0),
SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0,
priv,
SD25G_LANE_LANE_2B(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET
(params->cfg_dis_2ndorder),
SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER,
priv,
SD25G_LANE_LANE_2C(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn),
SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN,
priv,
SD25G_LANE_LANE_2E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET
(params->cfg_itx_ipcml_base_1_0),
SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0,
priv,
SD25G_LANE_LANE_00(sd_index));
sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET
(params->cfg_rx_reserve_7_0),
SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0,
priv,
SD25G_LANE_LANE_44(sd_index));
sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET
(params->cfg_rx_reserve_15_8),
SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8,
priv,
SD25G_LANE_LANE_45(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) |
SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0),
SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN |
SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0,
priv,
SD25G_LANE_LANE_0D(sd_index));
sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET
(params->cfg_vga_ctrl_byp_4_0),
SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0,
priv,
SD25G_LANE_LANE_21(sd_index));
sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET
(params->cfg_eqr_force_3_0),
SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0,
priv,
SD25G_LANE_LANE_22(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET
(params->cfg_eqc_force_3_0) |
SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd),
SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 |
SD25G_LANE_LANE_1C_LN_CFG_DFE_PD,
priv,
SD25G_LANE_LANE_1C(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET
(params->cfg_sum_setcm_en),
SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN,
priv,
SD25G_LANE_LANE_1E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET
(params->cfg_init_pos_iscan_6_0),
SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0,
priv,
SD25G_LANE_LANE_25(sd_index));
sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET
(params->cfg_init_pos_ipi_6_0),
SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0,
priv,
SD25G_LANE_LANE_26(sd_index));
sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),
SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,
priv,
SD25G_LANE_LANE_18(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET
(params->cfg_dfedig_m_2_0),
SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0,
priv,
SD25G_LANE_LANE_0E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig),
SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG,
priv,
SD25G_LANE_LANE_0E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) |
SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv),
SD25G_LANE_LANE_40_LN_R_TX_POL_INV |
SD25G_LANE_LANE_40_LN_R_RX_POL_INV,
priv,
SD25G_LANE_LANE_40(sd_index));
sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) |
SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en),
SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN |
SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN,
priv,
SD25G_LANE_LANE_04(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en),
SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN,
priv,
SD25G_LANE_LANE_1E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en),
SD25G_LANE_LANE_19_LN_CFG_TXLB_EN,
priv,
SD25G_LANE_LANE_19(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0),
SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
priv,
SD25G_LANE_LANE_2E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1),
SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,
priv,
SD25G_LANE_LANE_2E(sd_index));
sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0),
SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
priv,
SD_LANE_25G_SD_LANE_CFG(sd_index));
sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0),
SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
priv,
SD25G_LANE_LANE_1C(sd_index));
usleep_range(1000, 2000);
sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1),
SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,
priv,
SD25G_LANE_LANE_1C(sd_index));
usleep_range(10000, 20000);
sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),
SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
priv,
SD25G_LANE_CMU_FF(sd_index));
value = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index)));
value = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value);
if (value) {
dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value);
return -EINVAL;
}
value = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index)));
value = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value);
if (value != 0x1) {
dev_err(dev, "25G PMA Reset failed: 0x%x\n", value);
return -EINVAL;
}
sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1),
SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS,
priv,
SD25G_LANE_CMU_2A(sd_index));
sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0),
SD_LANE_25G_SD_SER_RST_SER_RST,
priv,
SD_LANE_25G_SD_SER_RST(sd_index));
sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0),
SD_LANE_25G_SD_DES_RST_DES_RST,
priv,
SD_LANE_25G_SD_DES_RST(sd_index));
sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),
SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
priv,
SD25G_LANE_CMU_FF(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET
(params->cfg_alos_thr_2_0),
SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0,
priv,
SD25G_LANE_LANE_2D(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0),
SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ,
priv,
SD25G_LANE_LANE_2E(sd_index));
sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0),
SD25G_LANE_LANE_2E_LN_CFG_PD_SQ,
priv,
SD25G_LANE_LANE_2E(sd_index));
return 0;
}