in microchip/sparx5_serdes.c [1416:1852]
static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd10g28_params *params)
{
struct sparx5_serdes_private *priv = macro->priv;
void __iomem **regs = priv->regs;
struct device *dev = priv->dev;
u32 lane_index = macro->sidx;
u32 sd_index = macro->stpidx;
void __iomem *sd_inst;
u32 value;
if (params->is_6g)
sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index);
else
sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index);
sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1),
SD_LANE_SD_LANE_CFG_MACRO_RST,
priv,
SD_LANE_SD_LANE_CFG(lane_index));
sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) |
SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) |
SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) |
SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) |
SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0),
SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT |
SD10G_LANE_LANE_93_R_REG_MANUAL |
SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT |
SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT |
SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL,
sd_inst,
SD10G_LANE_LANE_93(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) |
SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) |
SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) |
SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1),
SD10G_LANE_LANE_94_R_ISCAN_REG |
SD10G_LANE_LANE_94_R_TXEQ_REG |
SD10G_LANE_LANE_94_R_MISC_REG |
SD10G_LANE_LANE_94_R_SWING_REG,
sd_inst,
SD10G_LANE_LANE_94(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1),
SD10G_LANE_LANE_9E_R_RXEQ_REG,
sd_inst,
SD10G_LANE_LANE_9E(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) |
SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) |
SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1),
SD10G_LANE_LANE_A1_R_SSC_FROM_HWT |
SD10G_LANE_LANE_A1_R_CDR_FROM_HWT |
SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT,
sd_inst,
SD10G_LANE_LANE_A1(sd_index));
sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) |
SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel),
SD_LANE_SD_LANE_CFG_RX_REF_SEL |
SD_LANE_SD_LANE_CFG_TX_REF_SEL,
priv,
SD_LANE_SD_LANE_CFG(lane_index));
sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET
(params->cfg_lane_reserve_7_0),
SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0,
sd_inst,
SD10G_LANE_LANE_40(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET
(params->cfg_ssc_rtl_clk_sel),
SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL,
sd_inst,
SD10G_LANE_LANE_50(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET
(params->cfg_txrate_1_0) |
SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET
(params->cfg_rxrate_1_0),
SD10G_LANE_LANE_35_CFG_TXRATE_1_0 |
SD10G_LANE_LANE_35_CFG_RXRATE_1_0,
sd_inst,
SD10G_LANE_LANE_35(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET
(params->r_d_width_ctrl_2_0),
SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0,
sd_inst,
SD10G_LANE_LANE_94(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET
(params->cfg_pma_tx_ck_bitwidth_2_0),
SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0,
sd_inst,
SD10G_LANE_LANE_01(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET
(params->cfg_rxdiv_sel_2_0),
SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0,
sd_inst,
SD10G_LANE_LANE_30(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET
(params->r_pcs2pma_phymode_4_0),
SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0,
sd_inst,
SD10G_LANE_LANE_A2(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),
SD10G_LANE_LANE_13_CFG_CDRCK_EN,
sd_inst,
SD10G_LANE_LANE_13(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET
(params->cfg_dfeck_en) |
SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) |
SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET
(params->cfg_erramp_pd),
SD10G_LANE_LANE_23_CFG_DFECK_EN |
SD10G_LANE_LANE_23_CFG_DFE_PD |
SD10G_LANE_LANE_23_CFG_ERRAMP_PD,
sd_inst,
SD10G_LANE_LANE_23(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET
(params->cfg_dfetap_en_5_1),
SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1,
sd_inst,
SD10G_LANE_LANE_22(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET
(params->cfg_pi_DFE_en),
SD10G_LANE_LANE_1A_CFG_PI_DFE_EN,
sd_inst,
SD10G_LANE_LANE_1A(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |
SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) |
SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) |
SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET
(params->cfg_tap_adv_3_0),
SD10G_LANE_LANE_02_CFG_EN_ADV |
SD10G_LANE_LANE_02_CFG_EN_MAIN |
SD10G_LANE_LANE_02_CFG_EN_DLY |
SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0,
sd_inst,
SD10G_LANE_LANE_02(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),
SD10G_LANE_LANE_03_CFG_TAP_MAIN,
sd_inst,
SD10G_LANE_LANE_03(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET
(params->cfg_tap_dly_4_0),
SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0,
sd_inst,
SD10G_LANE_LANE_04(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET
(params->cfg_vga_ctrl_3_0),
SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0,
sd_inst,
SD10G_LANE_LANE_2F(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET
(params->cfg_vga_cp_2_0),
SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0,
sd_inst,
SD10G_LANE_LANE_2F(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET
(params->cfg_eq_res_3_0),
SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0,
sd_inst,
SD10G_LANE_LANE_0B(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),
SD10G_LANE_LANE_0D_CFG_EQR_BYP,
sd_inst,
SD10G_LANE_LANE_0D(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET
(params->cfg_eq_c_force_3_0) |
SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET
(params->cfg_sum_setcm_en),
SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 |
SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN,
sd_inst,
SD10G_LANE_LANE_0E(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET
(params->cfg_en_dfedig),
SD10G_LANE_LANE_23_CFG_EN_DFEDIG,
sd_inst,
SD10G_LANE_LANE_23(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET
(params->cfg_en_preemph),
SD10G_LANE_LANE_06_CFG_EN_PREEMPH,
sd_inst,
SD10G_LANE_LANE_06(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET
(params->cfg_itx_ippreemp_base_1_0) |
SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET
(params->cfg_itx_ipdriver_base_2_0),
SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 |
SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0,
sd_inst,
SD10G_LANE_LANE_33(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET
(params->cfg_ibias_tune_reserve_5_0),
SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0,
sd_inst,
SD10G_LANE_LANE_52(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET
(params->cfg_txswing_half),
SD10G_LANE_LANE_37_CFG_TXSWING_HALF,
sd_inst,
SD10G_LANE_LANE_37(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET
(params->cfg_dis_2nd_order),
SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER,
sd_inst,
SD10G_LANE_LANE_3C(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET
(params->cfg_rx_ssc_lh),
SD10G_LANE_LANE_39_CFG_RX_SSC_LH,
sd_inst,
SD10G_LANE_LANE_39(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET
(params->cfg_pi_floop_steps_1_0),
SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0,
sd_inst,
SD10G_LANE_LANE_1A(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET
(params->cfg_pi_ext_dac_23_16),
SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16,
sd_inst,
SD10G_LANE_LANE_16(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET
(params->cfg_pi_ext_dac_15_8),
SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8,
sd_inst,
SD10G_LANE_LANE_15(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET
(params->cfg_iscan_ext_dac_7_0),
SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0,
sd_inst,
SD10G_LANE_LANE_26(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET
(params->cfg_cdr_kf_gen1_2_0),
SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0,
sd_inst,
SD10G_LANE_LANE_42(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET
(params->r_cdr_m_gen1_7_0),
SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0,
sd_inst,
SD10G_LANE_LANE_0F(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET
(params->cfg_pi_bw_gen1_3_0),
SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0,
sd_inst,
SD10G_LANE_LANE_24(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET
(params->cfg_pi_ext_dac_7_0),
SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0,
sd_inst,
SD10G_LANE_LANE_14(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),
SD10G_LANE_LANE_1A_CFG_PI_STEPS,
sd_inst,
SD10G_LANE_LANE_1A(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET
(params->cfg_mp_max_3_0),
SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0,
sd_inst,
SD10G_LANE_LANE_3A(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET
(params->cfg_rstn_dfedig),
SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG,
sd_inst,
SD10G_LANE_LANE_31(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET
(params->cfg_alos_thr_3_0),
SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0,
sd_inst,
SD10G_LANE_LANE_48(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET
(params->cfg_predrv_slewrate_1_0),
SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0,
sd_inst,
SD10G_LANE_LANE_36(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET
(params->cfg_itx_ipcml_base_1_0),
SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0,
sd_inst,
SD10G_LANE_LANE_32(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET
(params->cfg_ip_pre_base_1_0),
SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0,
sd_inst,
SD10G_LANE_LANE_37(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET
(params->cfg_lane_reserve_15_8),
SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8,
sd_inst,
SD10G_LANE_LANE_41(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET
(params->r_en_auto_cdr_rstn),
SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN,
sd_inst,
SD10G_LANE_LANE_9E(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET
(params->cfg_oscal_afe) |
SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET
(params->cfg_pd_osdac_afe),
SD10G_LANE_LANE_0C_CFG_OSCAL_AFE |
SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE,
sd_inst,
SD10G_LANE_LANE_0C(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
(params->cfg_resetb_oscal_afe[0]),
SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
sd_inst,
SD10G_LANE_LANE_0B(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET
(params->cfg_resetb_oscal_afe[1]),
SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,
sd_inst,
SD10G_LANE_LANE_0B(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET
(params->r_tx_pol_inv) |
SD10G_LANE_LANE_83_R_RX_POL_INV_SET
(params->r_rx_pol_inv),
SD10G_LANE_LANE_83_R_TX_POL_INV |
SD10G_LANE_LANE_83_R_RX_POL_INV,
sd_inst,
SD10G_LANE_LANE_83(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET
(params->cfg_rx2tx_lp_en) |
SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET
(params->cfg_tx2rx_lp_en),
SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN |
SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN,
sd_inst,
SD10G_LANE_LANE_06(sd_index));
sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |
SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en),
SD10G_LANE_LANE_0E_CFG_RXLB_EN |
SD10G_LANE_LANE_0E_CFG_TXLB_EN,
sd_inst,
SD10G_LANE_LANE_0E(sd_index));
sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0),
SD_LANE_SD_LANE_CFG_MACRO_RST,
priv,
SD_LANE_SD_LANE_CFG(lane_index));
sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
SD10G_LANE_LANE_50_CFG_SSC_RESETB,
sd_inst,
SD10G_LANE_LANE_50(sd_index));
sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),
SD10G_LANE_LANE_50_CFG_SSC_RESETB,
priv,
SD10G_LANE_LANE_50(sd_index));
sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100),
SD_LANE_MISC_SD_125_RST_DIS,
priv,
SD_LANE_MISC(lane_index));
sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100),
SD_LANE_MISC_RX_ENA,
priv,
SD_LANE_MISC(lane_index));
sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100),
SD_LANE_MISC_MUX_ENA,
priv,
SD_LANE_MISC(lane_index));
usleep_range(3000, 6000);
value = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index)));
value = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value);
if (value != 1) {
dev_err(dev, "10G PMA Reset failed: 0x%x\n", value);
return -EINVAL;
}
sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0),
SD_LANE_SD_SER_RST_SER_RST,
priv,
SD_LANE_SD_SER_RST(lane_index));
sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0),
SD_LANE_SD_DES_RST_DES_RST,
priv,
SD_LANE_SD_DES_RST(lane_index));
return 0;
}