in intel/phy-intel-thunderbay-emmc.c [308:431]
static int thunderbay_emmc_phy_power_on(struct phy *phy)
{
struct thunderbay_emmc_phy *tbh_phy = phy_get_drvdata(phy);
unsigned long rate;
/* Overwrite capability bits configurable in bootloader */
update_reg(tbh_phy, CTRL_CFG_0,
SUPPORT_HS_MASK, SUPPORT_HS_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_0,
SUPPORT_8B_MASK, SUPPORT_8B_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_1,
SUPPORT_SDR50_MASK, SUPPORT_SDR50_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_1,
SUPPORT_DDR50_MASK, SUPPORT_DDR50_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_1,
SUPPORT_SDR104_MASK, SUPPORT_SDR104_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_1,
SUPPORT_HS400_MASK, SUPPORT_HS400_SHIFT, 0x1);
update_reg(tbh_phy, CTRL_CFG_1,
SUPPORT_64B_MASK, SUPPORT_64B_SHIFT, 0x1);
if (tbh_phy->phy_power_sts == PHY_UNINITIALIZED) {
/* Indicates initialization, settings for init, same as 400KHZ setting */
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK, SEL_DLY_TXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK, SEL_DLY_RXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK, ITAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK, ITAP_DLY_SEL_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK, OTAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK, OTAP_DLY_SEL_SHIFT, 0);
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK, DLL_TRIM_ICP_SHIFT, 0);
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
} else if (tbh_phy->phy_power_sts == PHY_INITIALIZED) {
/* Indicates actual clock setting */
rate = clk_get_rate(tbh_phy->emmcclk);
switch (rate) {
case 200000000:
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
SEL_DLY_TXCLK_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
SEL_DLY_RXCLK_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
ITAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
ITAP_DLY_SEL_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
OTAP_DLY_ENA_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
OTAP_DLY_SEL_SHIFT, 2);
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
DLL_TRIM_ICP_SHIFT, 0x8);
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
DR_TY_SHIFT, 0x1);
/* For HS400 only */
update_reg(tbh_phy, PHY_CFG_2, SEL_STRB_MASK,
SEL_STRB_SHIFT, STRB);
break;
case 50000000 ... 52000000:
/* For both HS and DDR52 this setting works */
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
SEL_DLY_TXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
SEL_DLY_RXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
ITAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
ITAP_DLY_SEL_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
OTAP_DLY_ENA_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
OTAP_DLY_SEL_SHIFT, 4);
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
DLL_TRIM_ICP_SHIFT, 0x8);
update_reg(tbh_phy, PHY_CFG_0,
DR_TY_MASK, DR_TY_SHIFT, 0x1);
break;
case 400000:
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
SEL_DLY_TXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
SEL_DLY_RXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
ITAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
ITAP_DLY_SEL_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
OTAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
OTAP_DLY_SEL_SHIFT, 0);
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
DLL_TRIM_ICP_SHIFT, 0);
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK, DR_TY_SHIFT, 0x1);
break;
default:
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
SEL_DLY_TXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, SEL_DLY_RXCLK_MASK,
SEL_DLY_RXCLK_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_ENA_MASK,
ITAP_DLY_ENA_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, ITAP_DLY_SEL_MASK,
ITAP_DLY_SEL_SHIFT, 0x0);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_ENA_MASK,
OTAP_DLY_ENA_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, OTAP_DLY_SEL_MASK,
OTAP_DLY_SEL_SHIFT, 2);
update_reg(tbh_phy, PHY_CFG_0, DLL_TRIM_ICP_MASK,
DLL_TRIM_ICP_SHIFT, 0x8);
update_reg(tbh_phy, PHY_CFG_0, DR_TY_MASK,
DR_TY_SHIFT, 0x1);
break;
}
/* Reset, init seq called without phy_power_off, this indicates init seq */
tbh_phy->phy_power_sts = PHY_UNINITIALIZED;
}
update_reg(tbh_phy, PHY_CFG_0, RETRIM_EN_MASK, RETRIM_EN_SHIFT, 0x1);
update_reg(tbh_phy, PHY_CFG_0, RETRIM_MASK, RETRIM_SHIFT, 0x0);
return thunderbay_emmc_phy_power(phy, 1);
}