in microchip/sparx5_serdes.c [709:817]
static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd25g28_media_preset *media,
struct sparx5_sd25g28_mode_preset *mode,
struct sparx5_sd25g28_args *args,
struct sparx5_sd25g28_params *params)
{
u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth);
struct sparx5_sd25g28_params init = {
.r_d_width_ctrl_2_0 = iw,
.r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
.r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
.cfg_vco_div_mode_1_0 = mode->vco_div_mode,
.cfg_pre_divsel_1_0 = mode->pre_divsel,
.cfg_sel_div_3_0 = mode->sel_div,
.cfg_vco_start_code_3_0 = 0,
.cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,
.cfg_tx_prediv_1_0 = mode->tx_pre_div,
.cfg_rxdiv_sel_2_0 = mode->ck_bitwidth,
.cfg_tx_subrate_2_0 = mode->subrate,
.cfg_rx_subrate_2_0 = mode->subrate,
.r_multi_lane_mode = 0,
.cfg_cdrck_en = 1,
.cfg_dfeck_en = mode->dfe_enable,
.cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1,
.cfg_dfedmx_pd = 1,
.cfg_dfetap_en_5_1 = mode->dfe_tap,
.cfg_dmux_pd = 0,
.cfg_dmux_clk_pd = 1,
.cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1,
.cfg_pi_DFE_en = mode->dfe_enable,
.cfg_pi_en = 1,
.cfg_pd_ctle = 0,
.cfg_summer_en = 1,
.cfg_pmad_ck_pd = 0,
.cfg_pd_clk = 0,
.cfg_pd_cml = 0,
.cfg_pd_driver = 0,
.cfg_rx_reg_pu = 1,
.cfg_pd_rms_det = 1,
.cfg_dcdr_pd = 0,
.cfg_ecdr_pd = 1,
.cfg_pd_sq = 1,
.cfg_itx_ipdriver_base_2_0 = mode->txmargin,
.cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
.cfg_tap_main = media->cfg_tap_main,
.cfg_en_main = media->cfg_en_main,
.cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
.cfg_en_adv = media->cfg_en_adv,
.cfg_en_dly = media->cfg_en_dly,
.cfg_iscan_en = 0,
.l1_pcs_en_fast_iscan = 0,
.l0_cfg_bw_1_0 = 0,
.cfg_en_dummy = 0,
.cfg_pll_reserve_3_0 = args->com_pll_reserve,
.l0_cfg_txcal_en = mode->com_txcal_en,
.l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb,
.l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb,
.cfg_tx_reserve_15_8 = mode->tx_reserve_msb,
.cfg_tx_reserve_7_0 = mode->tx_reserve_lsb,
.cfg_bw_1_0 = mode->bw,
.cfg_txcal_man_en = 1,
.cfg_phase_man_4_0 = 0,
.cfg_quad_man_1_0 = 0,
.cfg_txcal_shift_code_5_0 = 2,
.cfg_txcal_valid_sel_3_0 = 4,
.cfg_txcal_en = 0,
.cfg_cdr_kf_2_0 = 1,
.cfg_cdr_m_7_0 = 6,
.cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0,
.cfg_pi_steps_1_0 = 0,
.cfg_dis_2ndorder = 1,
.cfg_ctle_rstn = mode->cfg_ctle_rstn,
.r_dfe_rstn = mode->r_dfe_rstn,
.cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0,
.cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base,
.cfg_rx_reserve_7_0 = 0xbf,
.cfg_rx_reserve_15_8 = 0x61,
.cfg_rxterm_2_0 = mode->rxterm,
.cfg_fom_selm = 0,
.cfg_rx_sp_ctle_1_0 = 0,
.cfg_isel_ctle_1_0 = 0,
.cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0,
.cfg_vga_byp = 1,
.cfg_agc_adpt_byp = 1,
.cfg_eqr_byp = 1,
.cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0,
.cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0,
.cfg_sum_setcm_en = 1,
.cfg_pi_dfe_en = 1,
.cfg_init_pos_iscan_6_0 = 6,
.cfg_init_pos_ipi_6_0 = 9,
.cfg_dfedig_m_2_0 = 6,
.cfg_en_dfedig = mode->dfe_enable,
.r_d_width_ctrl_from_hwt = 0,
.r_reg_manual = 1,
.reg_rst = args->reg_rst,
.cfg_jc_byp = 1,
.cfg_common_reserve_7_0 = 1,
.cfg_pll_lol_set = 1,
.cfg_tx2rx_lp_en = 0,
.cfg_txlb_en = 0,
.cfg_rx2tx_lp_en = 0,
.cfg_rxlb_en = 0,
.r_tx_pol_inv = args->txinvert,
.r_rx_pol_inv = args->rxinvert,
};
*params = init;
}