in rockchip/phy-rockchip-inno-dsidphy.c [289:445]
static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
{
struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
const struct {
unsigned long rate;
u8 hs_prepare;
u8 clk_lane_hs_zero;
u8 data_lane_hs_zero;
u8 hs_trail;
} timings[] = {
{ 110000000, 0x20, 0x16, 0x02, 0x22},
{ 150000000, 0x06, 0x16, 0x03, 0x45},
{ 200000000, 0x18, 0x17, 0x04, 0x0b},
{ 250000000, 0x05, 0x17, 0x05, 0x16},
{ 300000000, 0x51, 0x18, 0x06, 0x2c},
{ 400000000, 0x64, 0x19, 0x07, 0x33},
{ 500000000, 0x20, 0x1b, 0x07, 0x4e},
{ 600000000, 0x6a, 0x1d, 0x08, 0x3a},
{ 700000000, 0x3e, 0x1e, 0x08, 0x6a},
{ 800000000, 0x21, 0x1f, 0x09, 0x29},
{1000000000, 0x09, 0x20, 0x09, 0x27},
};
u32 t_txbyteclkhs, t_txclkesc;
u32 txbyteclkhs, txclkesc, esc_clk_div;
u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
unsigned int i;
inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
/* Select MIPI mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
/* Configure PLL */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
/* Enable PLL and LDO */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
REG_LDOPD_MASK | REG_PLLPD_MASK,
REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
/* Reset analog */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
REG_SYNCRST_MASK, REG_SYNCRST_RESET);
udelay(1);
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
/* Reset digital */
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
udelay(1);
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
txbyteclkhs = inno->pll.rate / 8;
t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
txclkesc = txbyteclkhs / esc_clk_div;
t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
/*
* The value of counter for HS Ths-exit
* Ths-exit = Tpin_txbyteclkhs * value
*/
hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
/*
* The value of counter for HS Tclk-post
* Tclk-post = Tpin_txbyteclkhs * value
*/
clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
/*
* The value of counter for HS Tclk-pre
* Tclk-pre = Tpin_txbyteclkhs * value
*/
clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs);
/*
* The value of counter for HS Tlpx Time
* Tlpx = Tpin_txbyteclkhs * (2 + value)
*/
lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
if (lpx >= 2)
lpx -= 2;
/*
* The value of counter for HS Tta-go
* Tta-go for turnaround
* Tta-go = Ttxclkesc * value
*/
ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
/*
* The value of counter for HS Tta-sure
* Tta-sure for turnaround
* Tta-sure = Ttxclkesc * value
*/
ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
/*
* The value of counter for HS Tta-wait
* Tta-wait for turnaround
* Tta-wait = Ttxclkesc * value
*/
ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
for (i = 0; i < ARRAY_SIZE(timings); i++)
if (inno->pll.rate <= timings[i].rate)
break;
if (i == ARRAY_SIZE(timings))
--i;
hs_prepare = timings[i].hs_prepare;
hs_trail = timings[i].hs_trail;
clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
data_lane_hs_zero = timings[i].data_lane_hs_zero;
wakeup = 0x3ff;
for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
if (i == REGISTER_PART_CLOCK_LANE)
hs_zero = clk_lane_hs_zero;
else
hs_zero = data_lane_hs_zero;
phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
T_LPX_CNT(lpx));
phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
T_HS_PREPARE_CNT(hs_prepare));
phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
T_HS_ZERO_CNT(hs_zero));
phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
T_HS_TRAIL_CNT(hs_trail));
phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
T_HS_EXIT_CNT(hs_exit));
phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
T_CLK_POST_CNT(clk_post));
phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
T_CLK_PRE_CNT(clk_pre));
phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
T_WAKEUP_CNT_HI(wakeup >> 8));
phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
T_WAKEUP_CNT_LO(wakeup));
phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
T_TA_GO_CNT(ta_go));
phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
T_TA_SURE_CNT(ta_sure));
phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
T_TA_WAIT_CNT(ta_wait));
}
/* Enable all lanes on analog part */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
LANE_EN_1 | LANE_EN_0);
}