in microchip/sparx5_serdes.c [819:923]
static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd10g28_media_preset *media,
struct sparx5_sd10g28_mode_preset *mode,
struct sparx5_sd10g28_args *args,
struct sparx5_sd10g28_params *params)
{
u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth);
struct sparx5_sd10g28_params init = {
.skip_cmu_cfg = args->skip_cmu_cfg,
.is_6g = args->is_6g,
.cmu_sel = mode->cmu_sel,
.cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6,
.cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2),
.cfg_lane_reserve_15_8 = mode->duty_cycle,
.cfg_txrate_1_0 = mode->rate,
.cfg_rxrate_1_0 = mode->rate,
.fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX,
.r_d_width_ctrl_2_0 = iw,
.cfg_pma_tx_ck_bitwidth_2_0 = iw,
.cfg_rxdiv_sel_2_0 = iw,
.r_pcs2pma_phymode_4_0 = 0,
.cfg_lane_id_2_0 = 0,
.cfg_cdrck_en = 1,
.cfg_dfeck_en = mode->dfe_enable,
.cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1,
.cfg_dfetap_en_5_1 = mode->dfe_tap,
.cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1,
.cfg_pi_DFE_en = mode->dfe_enable,
.cfg_pi_en = 1,
.cfg_pd_ctle = 0,
.cfg_summer_en = 1,
.cfg_pd_rx_cktree = 0,
.cfg_pd_clk = 0,
.cfg_pd_cml = 0,
.cfg_pd_driver = 0,
.cfg_rx_reg_pu = 1,
.cfg_d_cdr_pd = 0,
.cfg_pd_sq = mode->dfe_enable,
.cfg_rxdet_en = 0,
.cfg_rxdet_str = 0,
.r_multi_lane_mode = 0,
.cfg_en_adv = media->cfg_en_adv,
.cfg_en_main = 1,
.cfg_en_dly = media->cfg_en_dly,
.cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
.cfg_tap_main = media->cfg_tap_main,
.cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
.cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0,
.cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0,
.cfg_eq_res_3_0 = media->cfg_eq_res_3_0,
.cfg_eq_r_byp = media->cfg_eq_r_byp,
.cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0,
.cfg_en_dfedig = mode->dfe_enable,
.cfg_sum_setcm_en = 1,
.cfg_en_preemph = 0,
.cfg_itx_ippreemp_base_1_0 = 0,
.cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6),
.cfg_ibias_tune_reserve_5_0 = (args->txswing & 63),
.cfg_txswing_half = (args->txmargin),
.cfg_dis_2nd_order = 0x1,
.cfg_rx_ssc_lh = 0x0,
.cfg_pi_floop_steps_1_0 = 0x0,
.cfg_pi_ext_dac_23_16 = (1 << 5),
.cfg_pi_ext_dac_15_8 = (0 << 6),
.cfg_iscan_ext_dac_7_0 = (1 << 7) + 9,
.cfg_cdr_kf_gen1_2_0 = 1,
.cfg_cdr_kf_gen2_2_0 = 1,
.cfg_cdr_kf_gen3_2_0 = 1,
.cfg_cdr_kf_gen4_2_0 = 1,
.r_cdr_m_gen1_7_0 = 4,
.cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1,
.cfg_pi_bw_gen2 = mode->pi_bw_gen1,
.cfg_pi_bw_gen3 = mode->pi_bw_gen1,
.cfg_pi_bw_gen4 = mode->pi_bw_gen1,
.cfg_pi_ext_dac_7_0 = 3,
.cfg_pi_steps = 0,
.cfg_mp_max_3_0 = 1,
.cfg_rstn_dfedig = mode->dfe_enable,
.cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0,
.cfg_predrv_slewrate_1_0 = 3,
.cfg_itx_ipcml_base_1_0 = 0,
.cfg_ip_pre_base_1_0 = 0,
.r_cdr_m_gen2_7_0 = 2,
.r_cdr_m_gen3_7_0 = 2,
.r_cdr_m_gen4_7_0 = 2,
.r_en_auto_cdr_rstn = 0,
.cfg_oscal_afe = 1,
.cfg_pd_osdac_afe = 0,
.cfg_resetb_oscal_afe[0] = 0,
.cfg_resetb_oscal_afe[1] = 1,
.cfg_center_spreading = 0,
.cfg_m_cnt_maxval_4_0 = 15,
.cfg_ncnt_maxval_7_0 = 32,
.cfg_ncnt_maxval_10_8 = 6,
.cfg_ssc_en = 1,
.cfg_tx2rx_lp_en = 0,
.cfg_txlb_en = 0,
.cfg_rx2tx_lp_en = 0,
.cfg_rxlb_en = 0,
.r_tx_pol_inv = args->txinvert,
.r_rx_pol_inv = args->rxinvert,
};
*params = init;
}